【摘要】：數(shù)據(jù)發(fā)生器作為現(xiàn)代測(cè)試與控制中常用的信號(hào)源,它可以產(chǎn)生具有一定編碼規(guī)則的用戶(hù)數(shù)據(jù),用來(lái)滿(mǎn)足特定數(shù)據(jù)測(cè)試要求。隨著現(xiàn)代科技水平的快速發(fā)展,待測(cè)設(shè)備的工作速度不斷提高以及系統(tǒng)功能更加復(fù)雜化,相應(yīng)的對(duì)數(shù)據(jù)發(fā)生器提出了高數(shù)據(jù)率、深存儲(chǔ)度、可編程能力、多觸發(fā)方式、皮秒定時(shí)等要求。本課題研究高速數(shù)據(jù)流合成技術(shù),完成高速可定時(shí)數(shù)據(jù)合成模塊設(shè)計(jì),最終實(shí)現(xiàn)2.7Gbps串行數(shù)據(jù)流輸出和單通道256Mbits存儲(chǔ)深度的雙通道高速數(shù)據(jù)流合成系統(tǒng)。高速可定時(shí)數(shù)據(jù)合成模塊作為數(shù)據(jù)發(fā)生器的核心單元,擔(dān)負(fù)著實(shí)現(xiàn)儀器的大部分功能和指標(biāo)的任務(wù)。主要包括:產(chǎn)生兩通道串行數(shù)據(jù)流信號(hào),實(shí)現(xiàn)重復(fù)、單次、單步三種工作模式以及數(shù)據(jù)率、定時(shí)延遲參數(shù)均可調(diào)的功能。本文闡述了如何產(chǎn)生數(shù)據(jù)率高、存儲(chǔ)深度深并工作在多種模式下的無(wú)縫數(shù)據(jù)流。具體工作內(nèi)容如下:(1)闡述高速數(shù)據(jù)流合成的基本原理和方法,結(jié)合功能和指標(biāo)要求,分析高速數(shù)據(jù)流合成的設(shè)計(jì)難點(diǎn),提出高速可定時(shí)數(shù)據(jù)合成模塊的總體設(shè)計(jì)方案。(2)完成時(shí)鐘單元電路設(shè)計(jì),采用DDS和鎖相環(huán)相結(jié)合的方式實(shí)現(xiàn)頻率范圍為50KHz~2.7GHz的差分時(shí)鐘輸出。(3)完成數(shù)據(jù)合成和控制單元電路。采用DDR存儲(chǔ)技術(shù)并結(jié)合FIFO緩沖數(shù)據(jù)的方法,完成無(wú)縫深存儲(chǔ)數(shù)據(jù)的產(chǎn)生。其中以DDR存儲(chǔ)器的大容量實(shí)現(xiàn)256Mbits的深存儲(chǔ),以FIFO的緩沖來(lái)完成數(shù)據(jù)的速率轉(zhuǎn)接和控制重部,利用并串轉(zhuǎn)換技術(shù)實(shí)現(xiàn)最高2.7Gbps數(shù)據(jù)率;采用高分辨率的可編程延遲線器件組來(lái)實(shí)現(xiàn)雙通道延遲定時(shí)的準(zhǔn)確性和高分辨率。(4)根據(jù)各單元模塊產(chǎn)生的信號(hào)波形測(cè)試圖,分析實(shí)際工作狀況。對(duì)在調(diào)試中遇見(jiàn)的問(wèn)題進(jìn)行分析,給出解決這些問(wèn)題所使用的方法。最后完成高速可定時(shí)數(shù)據(jù)合成模塊的測(cè)試與驗(yàn)收,并整理相關(guān)技術(shù)文檔。本文通過(guò)對(duì)上述重點(diǎn)技術(shù)的研究實(shí)現(xiàn),完成了高速可定時(shí)數(shù)據(jù)合成模塊的設(shè)計(jì)與調(diào)試,實(shí)現(xiàn)了在多種觸發(fā)方式和運(yùn)行模式下的高速數(shù)據(jù)流輸出,達(dá)到了設(shè)計(jì)所要求的目標(biāo)。
[Abstract]:As a common signal source in modern testing and control, data generator can generate user data with certain coding rules to meet the requirements of specific data testing. With the rapid development of modern science and technology, the working speed of the equipment to be tested has been improved and the system function has become more complicated. Accordingly, the high data rate, deep storage, programmable ability and multi-trigger mode are proposed for the data generator. Picosecond timing and other requirements. In this paper, the high speed data stream synthesis technology is studied, and the design of high speed timing data synthesis module is completed. Finally, a 2. 7Gbps serial data stream output and a single channel 256Mbits storage depth two channel high speed data stream synthesis system are realized. As the core unit of the data generator, the high speed timing data synthesis module is responsible for realizing most of the functions and targets of the instrument. It mainly includes: generating two channel serial data stream signals, realizing the functions of repeat, single, single step, data rate and timing delay parameters can be adjusted. This paper describes how to generate a seamless data stream with high data rate, deep storage depth and working in multiple modes. The main contents are as follows: (1) the basic principles and methods of high speed data stream synthesis are expounded, and the design difficulties of high speed data stream synthesis are analyzed according to the function and index requirements. The overall design scheme of high speed timing data synthesis module is presented. (2) the clock unit circuit is designed and the differential clock output with the frequency range of 50 KHz 2.7GHz is realized by combining DDS and PLL. (3) the data synthesis and control unit circuit is completed. Using DDR storage technology and FIFO buffer data, the generation of seamless deep storage data is completed. The DDR memory is used to realize 256Mbits deep storage, the FIFO buffer is used to complete the data rate transfer and control reconfiguration, and the data rate is up to 2.7Gbps using parallel string conversion technology. The high resolution programmable delay line device group is used to realize the accuracy and high resolution of dual channel delay timing. (4) according to the signal waveform test diagram generated by each unit module, the actual working condition is analyzed. The problems encountered in debugging are analyzed, and the methods to solve these problems are given. Finally, the test and acceptance of the high-speed timing data synthesis module are completed, and the related technical documents are arranged. Through the research and implementation of the above key technologies, the design and debugging of the high speed timing data synthesis module are completed, and the output of the high speed data stream under various trigger modes and operation modes is realized, and the goal of the design is achieved.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類(lèi)號(hào)】：TN929.53

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