本文選題：IQ數(shù)據(jù) + FPGA　； 參考：《北京郵電大學(xué)》2014年碩士論文

【摘要】：隨著科技不斷進(jìn)步,通信技術(shù)的不斷發(fā)展,對(duì)通信技術(shù)的研究工作持續(xù)進(jìn)行。TD-LTE(Time Division Long Term Evolution)作為我國研發(fā)的通信技術(shù)標(biāo)準(zhǔn)TD-SCDMA(Time Division-Synchronization Code Division Multiple Access)的長(zhǎng)期演進(jìn)技術(shù),我國在“新一代寬帶無線通信網(wǎng)”計(jì)劃中對(duì)TD-LTE研究做出了巨大投入。Ir接口協(xié)議是TD-LTE中基站設(shè)備和射頻設(shè)備之間的主要接口協(xié)議。深入研究Ir接口協(xié)議,對(duì)于完善協(xié)議功能,推進(jìn)TD-LTE的推廣具有重要意義。 本文為驗(yàn)證Ir接口對(duì)用戶IQ (In-phase Quadrature)數(shù)據(jù)的處理功能,需要將基站設(shè)備中CPRI核解析出的IQ數(shù)據(jù),實(shí)時(shí)高速傳輸至上位機(jī)進(jìn)行短時(shí)存儲(chǔ)。根據(jù)本項(xiàng)功能需求,本文設(shè)計(jì)實(shí)現(xiàn)IQ數(shù)據(jù)的高速傳輸模塊。主要的工作包括：采用從上到下,模塊化的設(shè)計(jì)思想對(duì)數(shù)據(jù)傳輸模塊進(jìn)行整體框架設(shè)計(jì)；采用改進(jìn)的異步FIFO對(duì)不同時(shí)鐘頻率下的IQ數(shù)據(jù)實(shí)現(xiàn)跨時(shí)鐘域同步,實(shí)現(xiàn)對(duì)不同CPRI線速率的自動(dòng)速率匹配；提出基于FPGA實(shí)現(xiàn)數(shù)據(jù)傳輸協(xié)議棧的方案,分層實(shí)現(xiàn)UDP/IP傳輸協(xié)議棧的傳輸層,網(wǎng)絡(luò)層和數(shù)據(jù)鏈路層協(xié)議的數(shù)據(jù)包封裝和向下層發(fā)送狀態(tài)機(jī),實(shí)現(xiàn)IQ數(shù)據(jù)高速實(shí)時(shí)發(fā)送： 本文為測(cè)試基站設(shè)備和射頻設(shè)備在IQ數(shù)據(jù)傳輸過程中的處理能力,需要對(duì)發(fā)送的IQ數(shù)據(jù)進(jìn)行高速緩存,對(duì)接收到的IQ數(shù)據(jù)進(jìn)行實(shí)時(shí)比對(duì),比對(duì)結(jié)果上報(bào)上位機(jī)。為此,本文設(shè)計(jì)并實(shí)現(xiàn)高速IQ數(shù)據(jù)緩存模塊,主要工作包括：突破傳統(tǒng)緩存方式,提出采用FPGA外部DDR3SDRAM和內(nèi)部BRAM相結(jié)合的方法,在PLB總線控制下,實(shí)現(xiàn)對(duì)IQ數(shù)據(jù)的高速緩存；利用FPGA內(nèi)部BRAM緩存實(shí)現(xiàn)對(duì)不同CPRI線速率條件下的IQ數(shù)據(jù)自動(dòng)速率匹配；提出全局輸入時(shí)鐘緩沖和數(shù)字時(shí)鐘管理單元相結(jié)合的時(shí)鐘設(shè)計(jì)方法,為高速IQ數(shù)據(jù)緩存模塊提供可靠的時(shí)鐘支持。采用PlanAhead對(duì)高速IQ數(shù)據(jù)緩存模塊的布局優(yōu)化設(shè)計(jì)。通過測(cè)試驗(yàn)證,本文所實(shí)現(xiàn)的高速數(shù)據(jù)接口模塊,可實(shí)現(xiàn)對(duì)IQ數(shù)據(jù)高速實(shí)時(shí)傳輸和高速緩存的功能,滿足功能需求指標(biāo)。
[Abstract]:With the progress of science and technology and the development of communication technology, the research work on communication technology has been carried out continuously. TD-LTEtime Division long term Evolution is the long-term evolution technology of TD-SCDMA-Time Division-Synchronization Code Division multiple access, which is developed in China. China has made a huge investment in the research of TD-LTE in the "New Generation Broadband Wireless Communication Network" project. The ir interface protocol is the main interface protocol between base station equipment and radio frequency equipment in TD-LTE. In order to improve the protocol function and promote the promotion of TD-LTE, it is of great significance to study the ir interface protocol in depth. In order to verify the processing function of ir interface to user IQ / In-phase Quadraturedata, we need to parse the IQ data from CPRI core in base station equipment. Real-time high-speed transmission to the host computer for short-time storage. According to the requirement of this function, this paper designs and implements the high-speed transmission module of IQ data. The main works are as follows: the whole frame of the data transmission module is designed with the idea of top-down and modularization, and the improved asynchronous FIFO is used to synchronize the IQ data at different clock frequencies across the clock domain. To realize the automatic rate matching of different CPRI line rates, the scheme of implementing data transmission protocol stack based on FPGA is proposed, and the transport layer of UDP / IP transmission protocol stack, the packet encapsulation of network layer and data link layer protocol and the sending state machine of data link layer protocol are implemented layer by layer. In order to test the processing ability of base station equipment and radio frequency equipment in the process of IQ data transmission, it is necessary to cache the transmitted IQ data and compare the received IQ data in real time. Compare the results to the upper computer. Therefore, this paper designs and implements the high-speed IQ data cache module. The main work includes: breaking through the traditional buffer mode, a method of combining DDR3 SDRAM with internal BRAM is put forward to realize the cache of IQ data under the control of PLB bus; Automatic rate matching of IQ data under different CPRI line rates is realized by using internal Bram buffer in FPGA, and a clock design method combining global input clock buffer and digital clock management unit is proposed. It provides reliable clock support for high speed IQ data cache module. Plan head is used to optimize the layout of high speed IQ data buffer module. The test results show that the high-speed data interface module of this paper can realize the function of high-speed real-time transmission and cache of IQ data, and meet the functional requirements.
【學(xué)位授予單位】：北京郵電大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN929.5;TN791

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本文編號(hào)：2004035