本文選題：全球定位系統(tǒng) + 印刷電路板�。� 參考：《上海交通大學(xué)》2014年碩士論文

【摘要】：隨著智能手機(jī)地興起,包括GPS天線在內(nèi)的多種天線被集成在了手機(jī)印刷電路板(后簡(jiǎn)稱PCB)上,同時(shí)CPU主頻達(dá)到1G赫茲,系統(tǒng)總線頻率更加接近GPS頻點(diǎn),高頻數(shù)字信號(hào)干擾射頻信號(hào)的可能性大大增加,即信號(hào)完整性問(wèn)題突出。本文研究了GPS天線被干擾的原因,發(fā)現(xiàn)了干擾源與雙倍速同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器(DDR SDRAM,后簡(jiǎn)稱DDR或RAM)總線振蕩頻率的相關(guān)性,對(duì)其做了詳細(xì)系統(tǒng)的分析,并提出了減少干擾的軟件優(yōu)化方法,明顯降低了對(duì)于GPS主頻點(diǎn)的干擾,提高了耦合靈敏度。在研究中發(fā)現(xiàn),RAM本身及其相關(guān)的頻率的多次或高次諧波,通過(guò)接口線,或者通過(guò)其他走線,會(huì)泄露串?dāng)_到GPS天線的工作頻點(diǎn)上。原因是噪聲信號(hào)在PCB走線中振蕩,會(huì)產(chǎn)生電磁場(chǎng)(帶電體產(chǎn)生電場(chǎng),帶電體的定向移動(dòng)產(chǎn)生磁場(chǎng)),耦合到GPS電路中時(shí),GPS電路中會(huì)產(chǎn)生一定量的偶合電壓,因?yàn)镚PS信號(hào)本來(lái)就很弱,所以少量的串?dāng)_偶合電壓就會(huì)影響到GPS性能。作者研究了幾個(gè)有效的軟件措施,包括天線附近測(cè)試點(diǎn)的處理;DDR頻率的修改;液晶屏(后簡(jiǎn)稱LCD)的移動(dòng)工業(yè)處理器接口(后簡(jiǎn)稱MIPI)傳輸時(shí)鐘的優(yōu)化;RAM驅(qū)動(dòng)能力調(diào)整等手段。經(jīng)過(guò)分析和試驗(yàn),作者提出了對(duì)LCD控制器的動(dòng)態(tài)存儲(chǔ)器訪問(wèn)(后簡(jiǎn)稱DMA)傳輸時(shí)的像素時(shí)鐘(后簡(jiǎn)稱PCLK)進(jìn)行修改,此方法有效。這些方法使硬件不用改板而保證性能,節(jié)約了成本。作者在第四章重點(diǎn)闡述了發(fā)現(xiàn)干擾源的實(shí)驗(yàn)過(guò)程,經(jīng)過(guò)層層排除和推斷,查到干擾的原因。在PCB板卡設(shè)計(jì)完畢,結(jié)構(gòu)堆疊和布局布線不能修改,而射頻調(diào)試、天線匹配也無(wú)效時(shí),修改驅(qū)動(dòng)軟件規(guī)避問(wèn)題成為實(shí)用的辦法。包括修改DDR的時(shí)鐘和驅(qū)動(dòng)能力、將空置的管腳配置為輸出低電平、修改MIPI頻率、修改LCDC傳輸頻率等方法。其中控制諧波盡量錯(cuò)開干擾頻點(diǎn)的思想得到了實(shí)驗(yàn)驗(yàn)證可行。在板卡級(jí)問(wèn)題以外,當(dāng)發(fā)現(xiàn)串?dāng)_和芯片內(nèi)部數(shù)字信號(hào)相關(guān)時(shí),我們找到了封裝導(dǎo)致的問(wèn)題源頭,說(shuō)明信號(hào)完整性問(wèn)題和芯片后端設(shè)計(jì)有關(guān)系,是個(gè)系統(tǒng)性全方位問(wèn)題,需要各方面的考慮和妥協(xié)。通過(guò)本次課題的分析和實(shí)踐發(fā)現(xiàn)其他天線干擾原因也有類似的情況。參考此文中的分析和實(shí)踐,芯片設(shè)計(jì)者可以對(duì)此類問(wèn)題有本質(zhì)的認(rèn)識(shí),未雨綢繆,提前做好芯片布局和后端設(shè)計(jì);嵌入式系統(tǒng)開發(fā)軟硬件人員可以在類似問(wèn)題中找到規(guī)避解決辦法。
[Abstract]:With the rise of smart phones, a variety of antennas, including GPS antennas, have been integrated on the printed circuit board of the mobile phone. At the same time, the main frequency of the CPU has reached 1G Hz, and the frequency of the system bus is closer to the GPS frequency. The possibility of interference with RF signals by high frequency digital signals is greatly increased, that is, the problem of signal integrity is prominent. In this paper, the reason of the interference of GPS antenna is studied, and the correlation between the interference source and the oscillation frequency of DDR SDRAM (or DDR or RAM) bus is found, and the systematic analysis of the interference source is made. A software optimization method to reduce the interference is proposed, which reduces the interference to the main frequency point of GPS and improves the coupling sensitivity. In the study, it is found that multiple or high order harmonics of the RAM itself and its associated frequencies may leak crosstalk to the working frequency of the GPS antenna through the interface line or other lines. The reason is that the noise signal oscillates in the PCB circuit, which will produce electromagnetic field (electric field produced by charged body, magnetic field produced by directional movement of charged body, coupling voltage of PCB circuit when coupled to GPS circuit. Because the GPS signal is weak, a small crosstalk coupling voltage will affect the GPS performance. Several effective software measures are studied, including the modification of DDR frequency at the test point near the antenna, the optimization of RAM drive capacity of the mobile industrial processor interface (MIPI) of liquid crystal screen (LCD) and so on. After analysis and experiment, the author proposes to modify the pixel clock (PCLK) in the dynamic memory access (DMA) transmission of the LCD controller. This method is effective. These methods ensure the performance of the hardware without changing the board and save the cost. In the fourth chapter, the author focuses on the experimental process of finding the interference source, and finds out the reason of the interference by removing and inferring it layer by layer. When the design of PCB card is finished, the structure stack and layout and wiring can not be modified, and the RF debugging and antenna matching are invalid, it becomes a practical method to modify the driving software to avoid the problem. It includes modifying the clock and driving ability of DDR, configuring the vacant pin to output low level, modifying MIPI frequency, modifying LCDC transmission frequency and so on. The idea of controlling harmonics to stagger the interference frequency as far as possible has been proved feasible by experiment. In addition to the card level problem, when the crosstalk is found to be related to the internal digital signal of the chip, we find the source of the problem caused by the encapsulation, which shows that the signal integrity problem is related to the design of the back end of the chip, and it is a systemic and omnidirectional problem. All aspects need to be considered and compromised. Through the analysis and practice of this subject, it is found that other antenna interference causes have similar situation. Referring to the analysis and practice in this paper, the chip designer can have the essential understanding to this kind of problem, make the plan in advance, do well the chip layout and the back-end design in advance; Embedded system development software and hardware personnel can find a solution to similar problems.
【學(xué)位授予單位】：上海交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN820

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