本文選題：QAM + 位同步��； 參考：《電子科技大學》2014年碩士論文

【摘要】：數(shù)字基帶通信系統(tǒng)接收端的基本功能是正確接收發(fā)送端傳來的數(shù)據(jù),完成與發(fā)送端對應的反變換,包括解調(diào),解密和譯碼等環(huán)節(jié),最后恢復出信源產(chǎn)生的數(shù)據(jù)交給信宿。接收端為了正確接收數(shù)據(jù),需要與發(fā)送端保持位定時的一致,信道的帶限特性會引起傳輸?shù)男盘柕拇a間干擾,給抽樣判決帶來影響。包括位同步算法和均衡算法在內(nèi)的基帶算法成為接收端的核心內(nèi)容,其中,位同步算法決定了基帶系統(tǒng)的位定時是否準確快速;均衡算法決定了數(shù)據(jù)在有碼間干擾的情況下能否正確傳輸,因此,研究基帶傳輸系統(tǒng)中的位同步和均衡具有重要的研究意義。本文基于FPGA的硬件平臺,研究和設計了在頻分雙工(Frequency Division Duplexing,FDD)傳輸模式下,以正交幅度調(diào)制(QAM)為信號調(diào)制方式,數(shù)據(jù)傳輸速率達到80Mbps的基帶傳輸系統(tǒng),并著重設計和實現(xiàn)了接收端的位同步算法以及盲均衡算法。本文的主要工作如下:首先介紹了基帶通信系統(tǒng)的整體框架,包括擾碼編碼、差分編碼、電平映射以及成型濾波模塊等。接著,詳細研究了和設計了基帶接收端的位同步算法以及盲均衡算法。針對位同步算法,先著重介紹了Gardner定時誤差檢測算法的基本原理,然后搭建位同步環(huán)路的Simulink模型,通過定點仿真確定合適的參數(shù)設置,最后用Verilog語言編寫相應的模塊,完成功能測試以及板級驗證;而盲均衡算法采用的是改進的雙模式恒模算法(MCADAMA),其設計思路和步驟與位同步模塊類似。在位同步算法和盲均衡算法實現(xiàn)的基礎上,本文進行了整個基帶傳輸系統(tǒng)在FPGA上的連調(diào)與測試。測試結(jié)果證明,本文中設計的位同步與盲均衡算法的實現(xiàn)方案是可行的,其達到的接收性能符合項目要求。
[Abstract]:The basic function of the receiver of the digital baseband communication system is to receive the data from the transmitter correctly, complete the inverse transformation corresponding to the transmitter, including demodulation, decryption and decoding, and finally restore the data generated by the source to the receiver. In order to receive the data correctly, the receiver needs to be consistent with the bit timing of the transmitter. The band-limit characteristic of the channel will cause the inter-symbol interference of the transmitted signal and affect the sampling decision. The base-band algorithm including bit synchronization algorithm and equalization algorithm becomes the core of the receiver. The bit synchronization algorithm determines whether the bit timing of the baseband system is accurate and fast. The equalization algorithm determines whether the data can be transmitted correctly in the presence of inter-symbol interference. Therefore, it is of great significance to study bit synchronization and equalization in baseband transmission systems. Based on the hardware platform of FPGA, this paper studies and designs a baseband transmission system with quadrature amplitude modulation (QAM) as signal modulation mode and data transmission rate up to 80Mbps in frequency division duplex Division duplex mode. The bit synchronization algorithm and blind equalization algorithm are designed and implemented. The main work of this paper is as follows: firstly, the whole frame of baseband communication system is introduced, including scrambling coding, differential coding, level mapping and shaping filter module. Then, the bit synchronization algorithm and blind equalization algorithm of baseband receiver are studied and designed in detail. For bit synchronization algorithm, the basic principle of Gardner timing error detection algorithm is introduced, then the Simulink model of bit synchronization loop is built, and the appropriate parameter setting is determined by fixed-point simulation. Finally, the corresponding module is written in Verilog language. The Blind equalization algorithm uses an improved dual-mode constant modulus algorithm, MCADAMAA, and its design idea and steps are similar to that of the bit synchronization module. Based on the realization of bit synchronization algorithm and blind equalization algorithm, the whole baseband transmission system is tested on FPGA. The test results show that the proposed bit-synchronization and blind equalization algorithm is feasible and the received performance meets the requirements of the project.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN914.3

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本文編號：1788783