本文選題：塊浮點 + 脈沖壓縮　； 參考：《西安電子科技大學》2014年碩士論文

【摘要】：雷達在現(xiàn)代軍用、民用的多個領域內起著主導作用,其中雷達信號處理的性能也起著比較關鍵的作用。隨著雷達信號處理和超大規(guī)模集成電路的不斷發(fā)展,為了適應多種工作環(huán)境和多種工作模式,為了能夠處理更大動態(tài)范圍內的數(shù)據(jù),并提高數(shù)據(jù)處理精度,雷達數(shù)字信號處理中的數(shù)據(jù)處理不再單純的采用定點數(shù)據(jù),而逐漸向浮點數(shù)據(jù)處理方向發(fā)展,但是浮點數(shù)據(jù)處理的硬件資源消耗比較大,在這種情況下,為了在一定程度上提高數(shù)據(jù)處理的動態(tài)范圍,塊浮點數(shù)據(jù)成為了平衡動態(tài)范圍和硬件面積的一種折中選擇。雷達信號處理中的脈沖壓縮技術解決了雷達發(fā)射信號功率與雷達距離分辨率之間的矛盾,因此得到了廣泛的應用。本文主要研究脈沖壓縮的硬件實現(xiàn)。本論文使用塊浮點數(shù)據(jù)格式,對雷達信號處理中的脈沖壓縮系統(tǒng)及其關鍵的快速傅里葉變換和逆變換(FFT/IFFT)的ASIC實現(xiàn)進行了設計和優(yōu)化。首先,介紹了雷達信號處理中的脈沖壓縮、FFT/IFFT的原理和塊浮點數(shù)據(jù)的硬件實現(xiàn)形式;然后結合FFT/IFFT的硬件實現(xiàn)原理,設計了適用于塊浮點數(shù)據(jù)處理的輸入輸出數(shù)據(jù)類型可配置,FFT/IFFT運算的點數(shù)可調整的FFT/IFFT IP核,并重點研究了減小硬件面積的數(shù)據(jù)存儲規(guī)律和塊浮點數(shù)據(jù)的處理過程,采用了內部數(shù)據(jù)倍頻處理的方式,使得系統(tǒng)的利用率提高并減小硬件面積。結合本設計的FFT/IFFT IP核,進行了輸入輸出數(shù)據(jù)類型可配置,處理數(shù)據(jù)長度可配置的塊浮點脈沖壓縮系統(tǒng)的規(guī)劃,并設計了一種脈沖壓縮的處理方法,研究了其存儲規(guī)律及其四路匹配相乘規(guī)律,從而減小了脈沖壓縮處理的延時,最終完成了四路可配置的塊浮點脈沖壓縮處理單元的RTL設計。本論文使用Matlab和Modelsim對設計的RTL級的四路脈沖壓縮塊浮點處理器進行了功能驗證;分析了FFT/IFFT單元的數(shù)據(jù)處理相對誤差在10-6數(shù)量級、信噪比在200 dB左右;同時對本設計的四通路脈沖壓縮系統(tǒng)的處理延時進行了分析;使用FPGA對其進行驗證;在SMIC 0.13μm工藝環(huán)境下,使用Design Compiler#174;進行邏輯綜合,該脈壓處理器的內部工作頻率為200 MHz,I/O系統(tǒng)時鐘頻率為100MHz;使用Formality#174;對邏輯綜合的網(wǎng)表進行了形式驗證,并使用Prime Time#174;對其進行了靜態(tài)時序分析。
[Abstract]:Radar plays a leading role in many fields of modern military and civil, among which the performance of radar signal processing also plays a key role. With the continuous development of radar signal processing and VLSI, in order to adapt to a variety of working environments and modes, to be able to process data in a larger dynamic range, and to improve the accuracy of data processing, The data processing in radar digital signal processing is no longer simply using fixed-point data, but gradually developing to floating-point data processing, but the hardware resources of floating-point data processing are relatively large, in this case, In order to improve the dynamic range of data processing to a certain extent, the block floating point data has become a compromise choice to balance the dynamic range and the hardware area. The pulse compression technique in radar signal processing solves the contradiction between the power of radar signal and the range resolution of radar, so it has been widely used. This paper mainly studies the hardware implementation of pulse compression. In this paper, the pulse compression system in radar signal processing and its key fast Fourier transform (FFT) and inverse transform (FT / IFFTFT) ASIC implementation are designed and optimized by using block floating-point data format. Firstly, the principle of pulse compression FFT / Ifft and the hardware realization of block floating-point data in radar signal processing are introduced, and then the hardware implementation principle of FFT/IFFT is combined. A configurable FFT/IFFT IP core suitable for block floating-point data processing is designed, which can be configured for FFT / Ifft operation. The rules of data storage for reducing hardware area and the processing process of block floating-point data are studied. The internal data frequency doubling method is used to improve the utilization ratio of the system and reduce the hardware area. Combined with the FFT/IFFT IP core designed in this paper, a block floating point pulse compression system with configurable input and output data type and configurable data length is designed, and a pulse compression processing method is designed. The storage law and the four-way matching multiplication rule are studied, which reduces the delay of pulse compression processing, and finally completes the RTL design of four-channel configurable block floating-point pulse compression processing unit. In this paper, Matlab and Modelsim are used to verify the function of the four-channel pulse compression block floating-point processor designed for RTL, and the relative error of data processing for FFT/IFFT unit is in the order of 10-6, and the SNR is about 200dB. At the same time, the processing delay of the four-way pulse compression system is analyzed, the FPGA is used to verify it, the Design Compiler #174 is used in the SMIC 0.13 渭 m process, and the logic synthesis is carried out. The internal working frequency of the pulse compression processor is 200 MHz / I / O system clock frequency is 100 MHz; the formal #174 is used; the network table of logic synthesis is formally verified and the Prime time #174 is used; the static timing analysis is carried out.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN957.51

【引證文獻】

相關會議論文 前1條

1 李偉;;一種可用于空間探測的塊浮點流水線FFT處理器[A];第二十四屆全國空間探測學術交流會論文摘要集[C];2011年

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本文編號：1778508