本文選題：現(xiàn)場可編程門陣列　切入點：雷達信號處理　出處：《西安電子科技大學(xué)》2014年碩士論文

【摘要】：近年來,隨著雷達及其相關(guān)領(lǐng)域技術(shù)的發(fā)展,雷達在人類生活及軍事中肩負起越來越重要的責任。雷達信號處理系統(tǒng)作為雷達系統(tǒng)的重要組成部分,近年來也隨著DSP和FPGA的大量引入發(fā)展迅速。特別是FPGA具備可并行處理、體積小、速度快等特點,在各數(shù)字系統(tǒng)中使用量大大增加。FPGA已經(jīng)具備實現(xiàn)整個雷達信號處理的能力,因此基于FPGA數(shù)字信號處理的實現(xiàn)在雷達信號處理中占有重要地位。本文針對FPGA在雷達系統(tǒng)設(shè)計中的應(yīng)用技術(shù)展開研究,主要講述三部分內(nèi)容:1.詳細介紹了雷達信號處理算法和多功能性設(shè)計�，F(xiàn)代雷達對其功能的要求越來越多樣化。針對這一要求,本文設(shè)計的信號處理系統(tǒng)可根據(jù)不同需求適時改變工作模式。針對不同的工作模式,各個信號處理算法參數(shù)可實現(xiàn)實時配置。隨后依次介紹了雷達信號處理的基本算法理論。重點研究了FIR實現(xiàn)自適應(yīng)MTD濾波器的設(shè)計方法,并進一步介紹了滑動MTD實現(xiàn)方法。2.詳細介紹了雷達信號處理檢測算法。雷達的根本任務(wù)是檢測目標,雷達信號處理的目的也是提高檢測概率。首先介紹了CFAR檢測的基本原理。然后按其處理方式分類分別研究了單元平均恒虛警檢測和雜波圖恒虛警檢測。針對單元平均恒虛警檢測分別研究了單元平均、單元平均選大、單元平均選小3種恒虛警處理方法,并進一步給出了其二維實現(xiàn)的方法。針對各恒虛警檢測方法,本文從檢測概率及檢測損失兩個方面分析了其各自的檢測性能。3.結(jié)合實際工程項目,詳細介紹了某雷達系統(tǒng)的FPGA設(shè)計。該雷達信號處理系統(tǒng)由AD定時采樣板及多塊信號處理板組成。信號處理由FPGA和DSP共同實現(xiàn)。FPGA完成定時控制、AD采樣、數(shù)字下變頻、脈沖壓縮、恒虛警檢測及與各雷達系統(tǒng)通信等工作。依次介紹了FPGA各模塊的程序設(shè)計及實現(xiàn)方法,重點描述了脈沖壓縮模塊和定時控制模塊。脈沖壓縮模塊采用分時復(fù)用FFT核的方法實現(xiàn)了多通道大數(shù)據(jù)量的脈沖壓縮處理。定時控制模塊實現(xiàn)了多工作模式雷達的復(fù)雜時序控制。經(jīng)過實驗室調(diào)試和外場實測驗證后,FPGA工作正常,信號處理系統(tǒng)實現(xiàn)了預(yù)期功能。
[Abstract]:In recent years, with the development of radar and its related technology, radar is shouldering more and more important responsibility in human life and military affairs. Radar signal processing system is an important part of radar system. In recent years, with the rapid development of DSP and FPGA, especially FPGA has the characteristics of parallel processing, small size, fast speed, and so on. The use of FPGA has been greatly increased in various digital systems. FPGA has the ability to realize the whole radar signal processing. Therefore, the realization of digital signal processing based on FPGA plays an important role in radar signal processing. In this paper, the application technology of FPGA in radar system design is studied. This paper introduces the radar signal processing algorithm and multifunctional design in detail. The requirements of modern radar for its functions are becoming more and more diversified. The signal processing system designed in this paper can change the working mode according to different demands. The parameters of each signal processing algorithm can be configured in real time. Then the basic algorithm theory of radar signal processing is introduced in turn. The design method of adaptive MTD filter based on FIR is studied emphatically. The realization method of sliding MTD. 2. The detection algorithm of radar signal processing is introduced in detail. The basic task of radar is to detect the target. The purpose of radar signal processing is also to improve the detection probability. Firstly, the basic principle of CFAR detection is introduced. Then, the unit average CFAR detection and clutter map CFAR detection are studied according to their processing methods. The average CFAR detection has studied the unit average, There are three CFAR processing methods, one is the average size of the unit and the other is the average selection of the unit, and the two dimensional realization method is also given, which is aimed at each CFAR detection method. This paper analyzes their detection performance from two aspects: detection probability and detection loss. The FPGA design of a radar system is introduced in detail. The radar signal processing system is composed of AD timing sampling board and multiple signal processing boards. The signal processing is implemented by FPGA and DSP to complete timing control AD sampling, digital downconversion, pulse compression, etc. CFAR detection and communication with radar systems are introduced. The program design and implementation method of each module of FPGA are introduced in turn. The pulse compression module and the timing control module are described in detail. The pulse compression module uses the time-sharing multiplexing FFT core to realize the pulse compression processing of the multi-channel large data volume. The timing control module realizes the multi-mode radar. After laboratory debugging and field testing, FPGA works normally. The signal processing system realizes the expected function.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN957.51;TN791

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