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萬兆FCoE監(jiān)控卡硬件的設(shè)計與實現(xiàn)

發(fā)布時間:2018-02-15 23:22

  本文關(guān)鍵詞: 萬兆FCoE 監(jiān)控 FPGA 出處:《電子科技大學》2014年碩士論文 論文類型:學位論文


【摘要】:隨著科學技術(shù)的飛速發(fā)展,信息、數(shù)據(jù)處理和互聯(lián)網(wǎng)等技術(shù)也逐漸融入到人們的日常工作和生活當中。對數(shù)據(jù)信息處理速度要求的不斷提高促使了數(shù)據(jù)中心的高速發(fā)展。數(shù)據(jù)中心中常見的網(wǎng)絡(luò)有最初的區(qū)域網(wǎng)絡(luò)(LAN)、存儲網(wǎng)絡(luò)(SAN)等,但前面兩者之間都有不足之處,此時就產(chǎn)生了融合兩者的FCo E技術(shù)。針對FCoE技術(shù)出現(xiàn)了融合網(wǎng)絡(luò)適配器(CNA)以及能處理FCoE的交換機、磁盤陣列、分析儀等。隨著這些設(shè)備的廣泛應(yīng)用,基于FCoE的網(wǎng)絡(luò)和設(shè)備之間的信息交互變得越來越復(fù)雜,同時對這些網(wǎng)絡(luò)和設(shè)備性能的要求也越來越高,而且這些設(shè)備的數(shù)據(jù)通信都不是透明的,為了能及時了解設(shè)備的通信情況,避免產(chǎn)生不必要的時間和經(jīng)濟損失,此時就需要能夠?qū)@些設(shè)備進行實時監(jiān)控。而針對FCoE網(wǎng)絡(luò)的監(jiān)控測試設(shè)備的研究就有一定的經(jīng)濟意義。本文研究的是基于萬兆FCoE的監(jiān)控卡,用于捕獲和分析萬兆FCoE網(wǎng)絡(luò)上的數(shù)據(jù)。本文的硬件部分主要是實時將從10G以太網(wǎng)鏈路上捕獲的數(shù)據(jù)通過PCI Epress 2.0總線寫入主機內(nèi)存,用于在主機界面上顯示抓獲的數(shù)據(jù)情況如數(shù)據(jù)類型、數(shù)據(jù)總量、接收數(shù)據(jù)速率等,以便于對此時設(shè)備的通信情況能夠?qū)崟r的了解。同時用戶能夠通過設(shè)置觸發(fā)條件和過濾規(guī)則控制底層硬件對接收到的幀進行觸發(fā)和過濾,這樣用戶可以提取所需要的幀而丟棄那些不需要的幀數(shù)據(jù),能夠節(jié)省時間提高工作效率。本文監(jiān)控卡的實現(xiàn)是基于FPGA的,采用Xilinx公司的Kintex-7XC7K325T開發(fā)板。本文先簡單介紹了光纖通道協(xié)議、萬兆以太網(wǎng)、FCoE協(xié)議、DMA技術(shù)和PCI Express總線技術(shù),通過分析監(jiān)控卡的功能需求提出了監(jiān)控卡的總體設(shè)計方案;對設(shè)計中的兩大部分FCoE接口和DMA控制器分別進行了詳細介紹,并對這兩個模塊通過Modelsim仿真工具進行了功能仿真;在功能仿真符合設(shè)計要求后,和軟件進行聯(lián)合測試,通過ISE工具將硬件代碼下載到開發(fā)板上和CNA卡或者是磁盤陣列、FCoE交換機相連,進行了詳細的分析和測試,通過Chipscope測試工具以及用戶界面得到的測試結(jié)果滿足了監(jiān)控卡的設(shè)計要求。
[Abstract]:With the rapid development of science and technology, information, Technologies such as data processing and the internet are gradually integrated into people's daily work and life. The increasing demand for the speed of data processing has promoted the rapid development of data centers. The common networks in data centers include:---. The original area network (LAN), the storage network (San), etc. However, there are some shortcomings between the two, and the FCoE technology that combines the two is produced. For the FCoE technology, there are converged network adapters and switches, disk arrays, which can handle FCoE. With the wide application of these devices, the information exchange between networks and devices based on FCoE becomes more and more complex, and the performance of these networks and devices is also becoming more and more demanding. Moreover, the data communication of these devices is not transparent. In order to understand the communication situation of the equipment in a timely manner and avoid unnecessary time and economic losses, At this time, we need to be able to monitor these devices in real time. And the research of monitoring and testing equipment for FCoE network has certain economic significance. The main hardware of this paper is to write the data captured from 10G Ethernet link to host memory through PCI Epress 2.0 bus in real time. Used to display captured data on the host interface such as data type, total amount of data, rate of receiving data, etc. At the same time, the user can control the bottom hardware to trigger and filter the received frame by setting the trigger condition and filtering rules. In this way, the user can extract the needed frames and discard the unnecessary frame data, which can save time and improve the efficiency. The implementation of this monitoring card is based on FPGA. This paper introduces the optical fiber channel protocol, Gigabit Ethernet FCoE protocol and PCI Express bus technology, and puts forward the overall design scheme of the monitoring card by analyzing the functional requirements of the monitoring card. The two parts of FCoE interface and DMA controller in the design are introduced in detail, and the two modules are simulated by Modelsim simulation tools, after the functional simulation meets the design requirements, the two modules are tested jointly with the software. The hardware code is downloaded to the development board by the ISE tool and connected to the CNA card or the disk array FCoE switch. It is analyzed and tested in detail. The test results obtained through the Chipscope test tool and the user interface meet the design requirements of the monitoring card.
【學位授予單位】:電子科技大學
【學位級別】:碩士
【學位授予年份】:2014
【分類號】:TN929.11

【參考文獻】

相關(guān)期刊論文 前1條

1 顏建峰;吳寧;;基于PCI總線的DMA高速數(shù)據(jù)傳輸系統(tǒng)[J];電子科技大學學報;2007年05期



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