本文關(guān)鍵詞：HEVC中的DCT硬件架構(gòu)設(shè)計(jì)與HLS實(shí)現(xiàn)研究　出處：《西安電子科技大學(xué)》2014年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： HEVC DCT HLS實(shí)現(xiàn)

【摘要】：ITU-T和ISO/IEC于2013年1月發(fā)布了一項(xiàng)新的視頻壓縮標(biāo)準(zhǔn)—HEVC。HEVC是繼H.264之后的新一代視頻壓縮標(biāo)準(zhǔn),與H.264相比,HEVC的壓縮效率高出一倍,HEVC標(biāo)準(zhǔn)的出現(xiàn)解決了視頻分辨率更高、視頻數(shù)據(jù)量更大、存儲(chǔ)和傳輸變得更加困難等難題。DCT變換在圖像視頻壓縮領(lǐng)域的應(yīng)用非常廣泛,作為視頻圖像壓縮的必要環(huán)節(jié),DCT算法是圖像視頻編碼算法中最活躍的研究部分之一。HEVC標(biāo)準(zhǔn)中的DCT變換是非常重要的預(yù)壓縮過程,由于HEVC標(biāo)準(zhǔn)中需要對(duì)視頻序列預(yù)測(cè)多個(gè)方向,然后通過壓縮反饋獲得最佳預(yù)測(cè)方向,因此需要多次執(zhí)行DCT部分,所以DCT的高效實(shí)現(xiàn)顯得十分重要。另外,HEVC對(duì)于整幅圖像有更為靈活的分塊機(jī)制,其中大尺寸的分塊也會(huì)為相應(yīng)尺寸的DCT變換帶來不便,因此對(duì)大尺寸DCT變換的硬件實(shí)現(xiàn)研究顯得尤為迫切。本文主要介紹了HEVC視頻壓縮編碼流程中的DCT變換過程,并針對(duì)HEVC中DCT的大尺寸計(jì)算這一點(diǎn),完成了兩種DCT硬件架構(gòu)的設(shè)計(jì)及HLS(High-level Synthesis)實(shí)現(xiàn)。本文的主要工作成果有:提出了以下兩種硬件架構(gòu)(1)基于矩陣相乘的DCT硬件架構(gòu)及實(shí)現(xiàn)。根據(jù)資源利用率、處理延遲以及數(shù)據(jù)吞吐率這三個(gè)指標(biāo)由HLS方法進(jìn)行綜合實(shí)現(xiàn)和優(yōu)化,使得綜合結(jié)果達(dá)到了5.56Gsps的數(shù)據(jù)吞吐率,滿足了4K視頻實(shí)時(shí)傳輸吞吐率。(2)基于蝶形算法的DCT硬件架構(gòu)及實(shí)現(xiàn)。根據(jù)蝶形算法的運(yùn)算原理,本文采用HLS方法對(duì)其進(jìn)行了設(shè)計(jì)實(shí)現(xiàn),與已有論文中DCT硬件結(jié)構(gòu)實(shí)現(xiàn)結(jié)果進(jìn)行了比較和分析。并以處理延遲以及數(shù)據(jù)吞吐率作為優(yōu)化目標(biāo)進(jìn)行HLS優(yōu)化設(shè)計(jì),所完成的實(shí)現(xiàn)綜合結(jié)果獲得了6.77Gsps的數(shù)據(jù)吞吐率,比已有文獻(xiàn)的實(shí)現(xiàn)結(jié)果相比獲得了更高的數(shù)據(jù)吞吐率,且該實(shí)現(xiàn)可以應(yīng)用于8K視頻實(shí)時(shí)壓縮。本文重點(diǎn)研究了HEVC中的整數(shù)DCT變換算法架構(gòu)設(shè)計(jì)、HLS實(shí)現(xiàn)及其關(guān)鍵技術(shù)。在設(shè)計(jì)過程中解決了資源利用率過高、處理延遲過大和數(shù)據(jù)吞吐率無法達(dá)到目標(biāo)值等問題;同時(shí)采用HLS方法完成了硬件實(shí)現(xiàn),解決了傳統(tǒng)硬件開發(fā)周期過長(zhǎng)的問題,并且能夠在一個(gè)軟件設(shè)計(jì)上不斷迭代出新的應(yīng)用在不同場(chǎng)景中的硬件架構(gòu)。最后對(duì)上述HLS實(shí)現(xiàn)分別完成了RTL功能仿真測(cè)試。其中,本文提出的硬件架構(gòu)和HLS實(shí)現(xiàn)方法可廣用于4K或8K分辨率視頻的實(shí)時(shí)壓縮。
[Abstract]:ITU-T and ISO/IEC in January 2013 released a new video compression standard - HEVC.HEVC H.264 is the second after the new generation of video compression standard, compared with H.264, HEVC compression efficiency is twice as high, HEVC standard solution with high resolution video, video data, storage and transmission become more difficult the problem of.DCT transform is widely used in the field of image and video compression, as a necessary part of video image compression, DCT algorithm is the DCT transform image encoding algorithm in the most active part of the research in.HEVC standard is very important to pre compression process, due to the need to predict the multiple directions of video sequence HEVC standard. Then through the feedback to obtain the best prediction direction compression, so you need DCT part of the implementation of many times, so the efficient implementation of DCT is very important. In addition, HEVC for the whole image is more flexible Block mechanism, the large size of the block will also bring inconvenience to the corresponding size of the DCT transform, so the large size DCT transform hardware research and implementation is particularly urgent. This paper mainly introduces the HEVC video compression encoding process of DCT transform process, and for the HEVC DCT in large size calculation of this point complete the design of two kinds of DCT and HLS hardware architecture (High-level Synthesis). The main contributions of this dissertation are: put forward the following two kinds of hardware architecture (1) and the realization of DCT hardware architecture based on matrix multiplication. According to the resource utilization rate, processing delay and throughput of the three indicators by the method of integrated HLS the implementation and optimization, makes the comprehensive results reached 5.56Gsps data throughput to meet the 4K real-time video transmission throughput. (2) and the realization of DCT hardware architecture based on butterfly algorithm. According to the operation principle of butterfly algorithm in this paper. The HLS method has carried on the design and implementation of DCT hardware structure, the existing results are compared and analyzed. And the processing delay and data throughput as the optimization goal for HLS optimization design, to achieve comprehensive results the obtained 6.77Gsps data throughput rate than the published results obtained and compared a higher data throughput, and the implementation of 8K can be applied to real-time video compression. This paper focuses on the architecture of integer DCT transform algorithm in HEVC design, HLS implementation and its key technology. In the design process to solve the resource utilization rate is too high, excessive processing delay and data throughput can reach the target value. At the same time; using HLS method to complete the hardware implementation, to solve the traditional hardware development cycle is too long, and can in a software design iteration of new applications in the same The hardware architecture of the scene. Finally, the RTL function simulation test is completed for the above HLS implementation. The hardware architecture and HLS implementation method proposed in this paper can be widely used for real-time compression of 4K or 8K resolution video.

【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN919.81

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