本文選題：FPGA + PCI　； 參考：《北方工業(yè)大學(xué)》2014年碩士論文

【摘要】：射電望遠(yuǎn)鏡在探測天體射電波的過程中會產(chǎn)生大量的數(shù)據(jù),如何將采集到的海量數(shù)據(jù)高速傳輸給計算機(jī)進(jìn)行分析和處理是一項(xiàng)巨大的挑戰(zhàn)。本論文在研究和分析現(xiàn)有的高速數(shù)據(jù)傳輸接口技術(shù)的前提下,將PCI Express，，總線技術(shù)作為研究對象,根據(jù)任務(wù)需求基于FPGA設(shè)計了一款采用PCI Express總線接口的高速數(shù)據(jù)傳輸系統(tǒng),并在計算機(jī)上開發(fā)了硬件設(shè)備的驅(qū)動程序和性能測試軟件。 論文首先介紹了現(xiàn)今的幾種高速數(shù)據(jù)傳輸接口技術(shù),并針對系統(tǒng)設(shè)計要求給出了基于PCI Express,總線技術(shù)的高速數(shù)據(jù)傳輸系統(tǒng)的設(shè)計方案。其次,深入研究了PCI Express總線協(xié)議,分別對PCI Express,總線的系統(tǒng)結(jié)構(gòu)、配置空間、分層結(jié)構(gòu)和總線事務(wù)進(jìn)行剖析,為接下來的設(shè)計提供了理論基礎(chǔ)。在FPGA中實(shí)現(xiàn)了PCI Express接口邏輯,通過PIO模式能夠?qū)?nèi)部寄存器進(jìn)行讀寫操作,并且驗(yàn)證了PCI Express存儲器讀、寫以及完成等事務(wù)的邏輯。數(shù)據(jù)傳輸使用DMA方式,詳細(xì)介紹了DMA引擎模塊的設(shè)計方法,對DMA寫和讀操作的操作流程進(jìn)行了透徹的分析和說明。最后,在計算機(jī)上針對PCI Express,總線接口開發(fā)設(shè)備的驅(qū)動程序,并且基于驅(qū)動程序設(shè)計性能測試軟件,實(shí)現(xiàn)了設(shè)備的狀態(tài)檢測、寄存器配置、DMA數(shù)據(jù)傳輸?shù)然竟δ堋?本設(shè)計采用PCI Express1.1標(biāo)準(zhǔn)的x8鏈路模式,經(jīng)過實(shí)際測試,DMA數(shù)據(jù)傳輸速度能達(dá)到約1400MB/s,滿足了系統(tǒng)的數(shù)據(jù)傳輸要求。
[Abstract]:Radio telescopes generate a large amount of data in the process of detecting radio waves from celestial bodies. It is a great challenge how to transmit the collected massive data to the computer at high speed for analysis and processing. In this paper, based on the research and analysis of the existing high-speed data transmission interface technology, the PCI Express, bus technology is taken as the research object, according to the task requirements based on FPGA, a high-speed data transmission system using PCI Express bus interface is designed. The hardware driver and performance testing software are developed on the computer. Firstly, several high speed data transmission interface technologies are introduced in this paper. The design scheme of high speed data transmission system based on PCI Express and bus technology is given. Secondly, the PCI Express bus protocol is deeply studied. The system structure, configuration space, layering structure and bus transaction of PCI Express and bus are analyzed respectively, which provides a theoretical basis for the next design. The PCI Express interface logic is implemented in FPGA, the internal register can be read and write by PIO mode, and the logic of reading, writing and completing transactions in PCI Express memory is verified. The design method of DMA engine module is introduced in detail, and the operation flow of DMA write and read operation is thoroughly analyzed and explained. Finally, the driver of the device is developed for PCI Express, bus interface on the computer, and the performance testing software is designed based on the driver to realize the state detection of the device. This design adopts the x8 link mode of PCI Express 1.1 standard. The speed of DMA data transmission can reach about 1400MB / s after the actual test, which meets the data transmission requirements of the system.
【學(xué)位授予單位】：北方工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TH751

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本文編號：2007446