【摘要】：本文提出了一種滿足多種協(xié)議要求的UHF RFID閱讀器接收機,包括:射頻前端和模擬基帶�；�0.18μm SiGeBiCMOS工藝,完成了接收機射頻前端以及模擬基帶中各模塊電路的分析與設計、版圖設計以及后仿真,主要成果如下:(1)通過文獻調(diào)研,了解UHF RFID閱讀器目前的發(fā)展和研究狀況。介紹了常見的幾種協(xié)議標準,包括:EPCGlobalC1G2、ISO/IEC18000-6C、美國FCC、歐洲ETSI以及我國關(guān)于射頻識別技術(shù)應用規(guī)定。根據(jù)協(xié)議標準制定了系統(tǒng)指標。(2)分析了經(jīng)典的接收機結(jié)構(gòu)及其優(yōu)點和不足。本文選擇結(jié)構(gòu)簡單,利于集成的直接變頻接收機結(jié)構(gòu)。(3)載波泄漏是UHF RFID閱讀器接收機設計的難點。本文分析了載波泄漏對接收機性能的影響,并提出了一種反饋式載波抵消射頻接收前端。分析了射頻前端的環(huán)路穩(wěn)定性、噪聲性能、線性度等關(guān)鍵指標。完成了各模塊的電路分析與設計。仿真結(jié)果顯示,在讀寫模式下,射頻前端的P1dB:-21.74dBm,噪聲系數(shù):22.57dB,功耗:145.4mW;在監(jiān)聽模式下,射頻前端的P1dB:-22.45dBm,噪聲系數(shù):11dB,功耗:70.88mW。(4)完成了模擬基帶電路的分析與設計。模擬基帶電路包括:前置放大器、八階Butterworth低通濾波器、自動頻率校準電路和直流偏移消除電路。仿真結(jié)果顯示,模擬基帶的增益范圍:10～70dB,步長為10dB;可實現(xiàn)四種截止頻率:250kHz、600kHz、1MHz、1.35MHz,在AFT電路協(xié)助下頻率偏差小于10%;在二倍頻處衰減度可達到40dB左右;總功耗29.568mW。
[Abstract]:In this paper, a UHF RFID reader receiver is proposed to meet the requirements of many protocols, including RF front-end and analog baseband. Based on 0.18 渭 m SiGeBiCMOS process, the analysis and design of RF front-end and analog baseband module circuit, layout design and post-simulation are completed. The main results are as follows: (1) through literature investigation, we can understand the current development and research status of UHF RFID reader. This paper introduces several common protocol standards, including EPCGlobalC1G2,ISO/IEC18000-6C, FCC, European ETSI and the application regulations of RFID technology in China. According to the protocol standard, the system index is established. (2) the classical receiver structure and its advantages and disadvantages are analyzed. In this paper, the structure of direct frequency conversion receiver is selected, which is simple in structure and convenient for integration. (3) Carrier leakage is a difficult point in the design of UHF RFID reader receiver. In this paper, the influence of carrier leakage on receiver performance is analyzed, and a feedback carrier cancellation RF receiver front end is proposed. The key indexes such as loop stability, noise performance and linearity of RF front end are analyzed. The circuit analysis and design of each module are completed. The simulation results show that in read and write mode, the P1dB 鈮，

本文編號：2506827