本文選題：路自適應(yīng) + 低功耗��； 參考：《計(jì)算機(jī)科學(xué)》2014年07期

【摘要】：如何提高多核處理器的性能和降低多核處理器中Cache的功耗已經(jīng)成為下一代多核處理器的研究熱點(diǎn)。為了降低片上多核處理器的功耗,基于路適應(yīng)算法可以采用一種新的動態(tài)劃分機(jī)制,該機(jī)制主要由路分配模塊和動態(tài)功耗控制模塊組成。路分配模塊在程序運(yùn)行過程中根據(jù)處理器核所運(yùn)行線程的工作集的大小調(diào)整處理器核所分配的Cache路。動態(tài)功耗控制模塊利用程序運(yùn)行的局部性原理,將處理器核所運(yùn)行線程的工作空間控制在少數(shù)Cache路中。關(guān)閉剩余的Cache路,從而達(dá)到降低Cache功耗的目的。該機(jī)制使用Simics全系統(tǒng)模擬平臺模擬多核處理器,并用SpecOMP測試集測試了系統(tǒng)的性能和功耗。與傳統(tǒng)的Cache(Conventional L2Cache,C-L2)相比,其IPC提高了9.27%,功耗降低了10.95%。
[Abstract]:How to improve the performance of multi-core processors and reduce the power consumption of Cache in multi-core processors has become the research hotspot of the next generation multi-core processors.In order to reduce the power consumption of multi-core processor on chip, a new dynamic partition mechanism can be adopted based on path adaptation algorithm, which is mainly composed of path allocation module and dynamic power control module.The path allocation module adjusts the Cache path allocated by the processor core according to the size of the working set of the thread run by the processor core during the running process of the program.The dynamic power control module controls the workspace of the threads run by the processor core in a few Cache paths using the principle of locality of the program.The remaining Cache circuit is closed to reduce the power consumption of Cache.The mechanism simulates the multi-core processor using Simics full-system simulation platform, and tests the performance and power consumption of the system with SpecOMP test set.Compared with the traditional Cache(Conventional L2CacheC-L2), its IPC increases 9.27% and its power consumption decreases 10.95%.
【作者單位】： 北京工業(yè)大學(xué)計(jì)算機(jī)學(xué)院;
【基金】：國家自然科學(xué)基金(61202076) 北京市教委科技計(jì)劃面上項(xiàng)目(KM201210005022)資助
【分類號】：TP332

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