本文選題：FPGA + 交通信號控制��； 參考：《長安大學(xué)》2014年碩士論文

【摘要】：隨著我國經(jīng)濟的發(fā)展和城市化進程的不斷加快，城市中的交通擁堵問題日益嚴(yán)重，交叉口處往往成為擁堵事件發(fā)生的高發(fā)區(qū),這直接影響到人們的日常出行活動。傳統(tǒng)交通控制器所廣泛采用的固定配時信號方案靈活性較差，已經(jīng)越來越不能滿足交叉口處的交通需求。因此設(shè)計出合理、高效和可靠的交通控制器系統(tǒng)對于改善和提高城市交通狀況具有重要意義。另外，交通控制系統(tǒng)發(fā)展的趨勢是更多具有智能化的特點。結(jié)合這些因素，本課題提出了一種基于FPGA的全感應(yīng)交通燈控制系統(tǒng)的設(shè)計方案。 本課題在研究了城市交通信號控制理論的基礎(chǔ)上，，提出以全感應(yīng)的方式控制交叉口處的信號燈。這種方式以各個方向上傳感器接收到的車流量數(shù)據(jù)為判斷依據(jù)，當(dāng)每個方向上都檢測到有車時則遵循定時控制規(guī)律，當(dāng)某個方向沒有車時則可跳過該相位，以避免無效時間等待。與定時控制方式相比，該方式具有一些智能化的特點，可以有效提高車輛通行效率。在設(shè)計上，主要包括軟件設(shè)計和硬件設(shè)計兩個方面。軟件方面首先根據(jù)設(shè)計上的功能要求，將系統(tǒng)拆分為各個子模塊，利用VHDL語言對子模塊進行功能描述，最后將各個模塊連成系統(tǒng)。硬件上設(shè)計了系統(tǒng)的整體框架結(jié)構(gòu)，并對系統(tǒng)中的重要模塊進行了原理圖設(shè)計和工作原理分析。系統(tǒng)整體的功能仿真結(jié)果表明該設(shè)計能夠?qū)崿F(xiàn)預(yù)期功能。
[Abstract]:With the development of economy and the acceleration of urbanization in our country, traffic congestion in cities is becoming more and more serious. Intersection often becomes a high incidence area of congestion events, which directly affects people's daily travel activities. The traditional traffic controller is widely used in the fixed timing signal scheme, which is less flexible, and can not meet the traffic demand of intersection more and more. Therefore, it is important to design a reasonable, efficient and reliable traffic controller system for improving urban traffic conditions. In addition, traffic control system development trend is more intelligent characteristics. Combined with these factors, this paper presents a design scheme of a fully inductive traffic light control system based on FPGA. Based on the study of the theory of urban traffic signal control, this paper proposes to control the signal lights at intersections in a fully inductive manner. This method is based on the traffic flow data received by sensors in various directions. When there is a vehicle detected in each direction, the timing control law is followed, and the phase can be skipped when there is no vehicle in a certain direction. To avoid waiting for invalid time. Compared with the timing control mode, this method has some intelligent features and can effectively improve the vehicle traffic efficiency. In the design, mainly includes the software design and the hardware design two aspects. Firstly, according to the functional requirements of the design, the system is divided into sub-modules, and the sub-modules are described by VHDL language. Finally, each module is connected into a system. The whole frame structure of the system is designed in hardware, and the schematic design and working principle analysis of the important modules in the system are carried out. The simulation results of the whole system show that the design can achieve the expected function.
【學(xué)位授予單位】：長安大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：U491.51

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本文編號：1819919