本文關(guān)鍵詞：基于FPGA的冷軋板形檢測(cè)儀實(shí)時(shí)信號(hào)采集處理系統(tǒng)設(shè)計(jì)　出處：《燕山大學(xué)》2016年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 板形檢測(cè) 實(shí)時(shí)信號(hào)處理 并行采樣 以太網(wǎng)通信 FIR濾波

【摘要】：冷軋板帶板形在線測(cè)量是現(xiàn)代軋制系統(tǒng)中關(guān)鍵的測(cè)量?jī)x器之一,而該方面的技術(shù)一直掌握在西門子、ABB等國(guó)外大公司手里,國(guó)內(nèi)在板形在線檢測(cè)方面的技術(shù)研究還存在較多問(wèn)題需要解決。鑒于上述原因,本文提出了采用FPGA技術(shù)對(duì)一種壓電式板形檢測(cè)儀進(jìn)行在線信號(hào)采集與處理的方案,對(duì)板形信號(hào)實(shí)時(shí)檢測(cè)與處理技術(shù)開展了深入的理論與實(shí)驗(yàn)研究,主要內(nèi)容包括:首先,在查閱大量國(guó)內(nèi)外現(xiàn)狀的基礎(chǔ)上,對(duì)冷軋板帶板形檢測(cè)儀的關(guān)鍵技術(shù)和存在的問(wèn)題進(jìn)行了綜述,并在此基礎(chǔ)上提出了基于FPGA的板形在線檢測(cè)與信號(hào)處理方案;其次,設(shè)計(jì)了板形檢測(cè)儀信號(hào)采集與處理系統(tǒng)的硬件電路,包括信號(hào)放大、濾波、AD轉(zhuǎn)換、FPGA主系統(tǒng)以及以太網(wǎng)接口電路等;然后,采用Verilog語(yǔ)言編程實(shí)現(xiàn)了對(duì)多路應(yīng)力信號(hào)的并行采樣控制。設(shè)計(jì)了基于加法樹結(jié)構(gòu)的FIR低通濾波器,和W5200以太網(wǎng)控制器的驅(qū)動(dòng)程序。最后,對(duì)所設(shè)計(jì)板形儀信號(hào)處理系統(tǒng)進(jìn)行了驗(yàn)證,結(jié)合Matlab和Modelsim軟件對(duì)FIR低通濾波器模塊進(jìn)行了仿真驗(yàn)證,并對(duì)系統(tǒng)的采樣結(jié)果進(jìn)行了標(biāo)定實(shí)驗(yàn),及在板形儀性能綜合測(cè)試平臺(tái)上對(duì)系統(tǒng)進(jìn)行了在線檢測(cè),并對(duì)實(shí)驗(yàn)結(jié)果及誤差進(jìn)行了分析。
[Abstract]:On-line measurement of cold rolled strip shape is one of the key measuring instruments in modern rolling system, and the technology in this field has been held in the hands of Siemens ABB and other large foreign companies. In China, there are still many problems to be solved in the field of on-line flatness detection, in view of the above reasons. In this paper, an on-line signal acquisition and processing scheme for a piezoelectric flatness detector using FPGA technology is proposed, and a deep theoretical and experimental study on the real-time detection and processing technology of flatness signal is carried out. The main contents include: firstly, on the basis of consulting a large number of domestic and foreign present situation, the key technology and existing problems of the cold-rolled strip shape detector are summarized. On the basis of this, the on-line flatness detection and signal processing scheme based on FPGA is put forward. Secondly, the hardware circuit of signal acquisition and processing system of flatness detector is designed, including signal amplification, filter AD converter FPGA main system and Ethernet interface circuit. Then, the parallel sampling control of multi-channel stress signal is realized by using Verilog programming language, and the FIR low-pass filter based on additive tree structure is designed. And W5200 Ethernet controller driver. Finally, the designed flatness instrument signal processing system is verified. Combined with Matlab and Modelsim software, the FIR low-pass filter module is simulated and validated, and the system sampling results are calibrated. The system is tested on the platform of flatness instrument, and the experimental results and error are analyzed.
【學(xué)位授予單位】：燕山大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TG334.9;TP274.2

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