SHA-less型流水線ADC的誤差分析及校準技術研究
發(fā)布時間：2019-06-28 18:01
【摘要】：模數(shù)轉換器(ADC)是模擬信號和數(shù)字信號處理系統(tǒng)的紐帶,隨著無線通訊快速發(fā)展,對ADC的要求也越來越高,人們希望在提升ADC的速度和精度的同時,盡可能的降低功耗。流水線ADC由于其流水的工作模式和特有的冗余位校正算法,在高速高精度的場合有廣泛應用,但流水線ADC較大的功耗成為其很嚴重的缺陷。無前端采樣保持電路(SHA-less)的流水線ADC可以節(jié)省大量的功耗,但也引入了一個嚴重的問題:ADC的第一級量化器要完成采樣保持的功能,由MDAC和Sub-ADC同時采樣動態(tài)的輸入信號,由于這兩個采樣通道之間不可避免的存在失配,再加上時鐘信號自身的影響,就導致了采樣失配誤差。這個誤差是SHA-less型流水線ADC必須解決的問題,尤其是對于中頻(IF)采樣應用,因為它嚴重惡化了ADC的高頻性能。本文所做的研究就致力于對這種流水線結構進行誤差分析和針對采樣失配誤差進行校正。論文分析了SHA-less型流水線ADC各種誤差源,包括噪聲,采樣保持電路誤差,運放誤差,Sub-ADC的誤差以及電容失配導致的誤差,以及SHA-less型流水線ADC特有的采樣失配誤差。論文結合一種基于tsmc 65nm實現(xiàn)的,12位SHA-less型高速流水線ADC,從三個方面分析了高速高精度的SHA-less流水線ADC主要的誤差源。分析了比較器的失調電壓,介紹了失調消除技術,最終確定了本設計所采用的三級預防大加鎖存器的低失調比較器結構,其中融合了輸入輸出失調消除技術。然后對電路的電容失配和熱噪聲進行了詳細的分析,并分別根據(jù)電路線性度和量化噪聲的約束,得到電路各電容的限制條件,并最終確定了電容的大小。最后著重分析了SHA-less流水線ADC中固有的Sub-ADC和MDAC之間的采樣失配誤差,采樣時刻偏差和采樣網(wǎng)絡帶寬失配是產生采樣失配誤差的原因,本文定量分析了這兩種誤差的影響,得出結論;采樣網(wǎng)絡帶寬失配在高頻時可以等效為一定大小采樣時刻偏差,而采樣時刻偏差導致的采樣誤差與輸入信號頻率成正比。對未經(jīng)過校準的12位250M流水線ADC進行仿真發(fā)現(xiàn),當正弦輸入信號頻率從11MHz增加到261MHz時,其SNDR從73.6dB下降到56.3dB,SFDR從88.7dB下降到56.5dB。仿真結果與分析結論一致,采樣失配誤差嚴重惡化了ADC的高頻性能。本文采用一種數(shù)字后臺校準算法來解決這一問題。本文采用的采樣失配誤差校準模塊包含三個電路單元,分別是:溢出檢測單元、數(shù)字控制單元、可變延時單元。溢出檢測單元檢測第一流水線級的輸出結果,將比較結果輸入數(shù)字控制單元,數(shù)字控制單元產生延時調節(jié)控制碼,產生的控制碼作為可變延時單元的輸入用來調節(jié)子ADC的采樣信號延時,通過多次迭代,使得子ADC的采樣時刻和MDAC采樣時刻對齊,整個模數(shù)轉換器可獲得良好的高頻性能。仿真結果顯示,數(shù)字校準算法有效抑制了輸入高頻信號時嚴重的奇次諧波,改善了ADC的高頻性能,使輸入信號頻率261MHz時,電路的SNDR提高到68.7dB,SFDR提高到77dB。在4倍內奎斯特頻率(600M)處,依然能夠保持60dB以上的SNDR,以及74dB的SFDR。經(jīng)過校準的SHA-less結構ADC具有良好的中頻采樣性能。2.5V模擬電壓1.2V數(shù)字電壓下,整個校準電路功耗3.1mW。本設計可校準的最大采樣時刻偏差可達到250ps,對于高速應用的流水線ADC來說,已經(jīng)足夠了。
[Abstract]:The analog-to-digital converter (ADC) is a link between the analog signal and the digital signal processing system. With the rapid development of the wireless communication, the requirements of the ADC are getting higher and higher, and it is desirable to reduce the power consumption as much as possible while improving the speed and accuracy of the ADC. The pipeline ADC has wide application in high-speed and high-precision applications due to its running mode and its unique redundancy bit correction algorithm, but the power consumption of the pipeline ADC is a very serious defect. a pipelined adc without a front-end sample-and-hold circuit (sha-less) can save a significant amount of power, but also introduces a serious problem: the first stage quantizer of the adc is to complete the function of the sample-hold, and the mdac and the sub-adc sample the dynamic input signal at the same time, Due to the inevitable mismatch between the two sampling channels, and the effect of the clock signal itself, the sample mismatch error is caused. This error is a problem that the SHA-less pipeline ADC must address, especially for intermediate frequency (IF) sampling applications, as it severely degrades the high frequency performance of the ADC. The research of this paper is devoted to the error analysis of such a pipeline and the correction of the error of the sample mismatch. The paper analyzes the various error sources of the SHA-less pipeline ADC, including the noise, the sample and hold circuit error, the operational amplifier error, the error of the Sub-ADC and the error caused by the capacitance mismatch, and the sample mismatch error characteristic of the SHA-less pipeline ADC. In this paper, a 12-bit SHA-less high-speed pipeline ADC based on tsmc 65 nm is combined, and the main error source of high-speed high-precision SHA-less pipeline ADC is analyzed from three aspects. The offset voltage of the comparator is analyzed, the offset cancellation technique is introduced, and the low-offset comparator structure of the three-stage prevention large-lock latch adopted in the design is finally determined, and the input-output offset cancellation technology is fused. And then the capacitance mismatch and the thermal noise of the circuit are analyzed in detail, and the limiting conditions of each capacitor of the circuit are obtained according to the linear degree of the circuit and the constraint of the quantization noise respectively, and the size of the capacitor is finally determined. In the end, the error of the sampling mismatch between the sub-ADC and the MDAC, which is inherent in the SHA-less pipeline ADC, is analyzed, and the sampling time deviation and the sample network bandwidth mismatch are the cause of the sampling mismatch error. The sampling network bandwidth mismatch can be equivalent to a certain size sampling time deviation at high frequency, and the sampling error caused by the sampling time deviation is directly proportional to the input signal frequency. It was found that the SNDR from 73.6 dB to 56.3 dB and the SFDR decreased from 88.7 dB to 56.5 dB when the frequency of the sinusoidal input signal increased from 11 MHz to 261 MHz. The result of the simulation is consistent with the analysis conclusion, and the sample mismatch error seriously deteriorates the high-frequency performance of the ADC. In this paper, a digital background calibration algorithm is used to solve this problem. The sample-mismatch error calibration module used in this paper consists of three circuit units, namely an overflow detection unit, a digital control unit and a variable delay unit. the overflow detection unit detects the output result of the first pipeline stage, the comparison result is input into the digital control unit, the digital control unit generates a time delay regulation control code, the generated control code is used as the input of the variable delay unit to adjust the sampling signal delay of the sub-ADC, So that the sampling time of the sub-ADC and the MDAC sampling time are aligned, and the whole analog-to-digital converter can obtain good high-frequency performance. The simulation results show that the digital calibration algorithm can effectively suppress the serious odd harmonics when the high-frequency signal is input, and the high-frequency performance of the ADC is improved. When the input signal frequency is 261MHz, the SNDR of the circuit is increased to 68.7 dB, and the SFDR is increased to 77 dB. The SNDR of more than 60 dB and the SFDR of 74 dB can still be maintained at 4 times the Nyquist frequency (600M). The calibrated SHA-less structure ADC has a good intermediate frequency sampling performance. The entire calibration circuit consumes 3.1 mW at a 2.5 V analog voltage of 1.2 V digital voltage. The maximum sampling time deviation of this design can be calibrated to 250 ps, which is sufficient for pipelined ADCs for high-speed applications.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN792
[Abstract]:The analog-to-digital converter (ADC) is a link between the analog signal and the digital signal processing system. With the rapid development of the wireless communication, the requirements of the ADC are getting higher and higher, and it is desirable to reduce the power consumption as much as possible while improving the speed and accuracy of the ADC. The pipeline ADC has wide application in high-speed and high-precision applications due to its running mode and its unique redundancy bit correction algorithm, but the power consumption of the pipeline ADC is a very serious defect. a pipelined adc without a front-end sample-and-hold circuit (sha-less) can save a significant amount of power, but also introduces a serious problem: the first stage quantizer of the adc is to complete the function of the sample-hold, and the mdac and the sub-adc sample the dynamic input signal at the same time, Due to the inevitable mismatch between the two sampling channels, and the effect of the clock signal itself, the sample mismatch error is caused. This error is a problem that the SHA-less pipeline ADC must address, especially for intermediate frequency (IF) sampling applications, as it severely degrades the high frequency performance of the ADC. The research of this paper is devoted to the error analysis of such a pipeline and the correction of the error of the sample mismatch. The paper analyzes the various error sources of the SHA-less pipeline ADC, including the noise, the sample and hold circuit error, the operational amplifier error, the error of the Sub-ADC and the error caused by the capacitance mismatch, and the sample mismatch error characteristic of the SHA-less pipeline ADC. In this paper, a 12-bit SHA-less high-speed pipeline ADC based on tsmc 65 nm is combined, and the main error source of high-speed high-precision SHA-less pipeline ADC is analyzed from three aspects. The offset voltage of the comparator is analyzed, the offset cancellation technique is introduced, and the low-offset comparator structure of the three-stage prevention large-lock latch adopted in the design is finally determined, and the input-output offset cancellation technology is fused. And then the capacitance mismatch and the thermal noise of the circuit are analyzed in detail, and the limiting conditions of each capacitor of the circuit are obtained according to the linear degree of the circuit and the constraint of the quantization noise respectively, and the size of the capacitor is finally determined. In the end, the error of the sampling mismatch between the sub-ADC and the MDAC, which is inherent in the SHA-less pipeline ADC, is analyzed, and the sampling time deviation and the sample network bandwidth mismatch are the cause of the sampling mismatch error. The sampling network bandwidth mismatch can be equivalent to a certain size sampling time deviation at high frequency, and the sampling error caused by the sampling time deviation is directly proportional to the input signal frequency. It was found that the SNDR from 73.6 dB to 56.3 dB and the SFDR decreased from 88.7 dB to 56.5 dB when the frequency of the sinusoidal input signal increased from 11 MHz to 261 MHz. The result of the simulation is consistent with the analysis conclusion, and the sample mismatch error seriously deteriorates the high-frequency performance of the ADC. In this paper, a digital background calibration algorithm is used to solve this problem. The sample-mismatch error calibration module used in this paper consists of three circuit units, namely an overflow detection unit, a digital control unit and a variable delay unit. the overflow detection unit detects the output result of the first pipeline stage, the comparison result is input into the digital control unit, the digital control unit generates a time delay regulation control code, the generated control code is used as the input of the variable delay unit to adjust the sampling signal delay of the sub-ADC, So that the sampling time of the sub-ADC and the MDAC sampling time are aligned, and the whole analog-to-digital converter can obtain good high-frequency performance. The simulation results show that the digital calibration algorithm can effectively suppress the serious odd harmonics when the high-frequency signal is input, and the high-frequency performance of the ADC is improved. When the input signal frequency is 261MHz, the SNDR of the circuit is increased to 68.7 dB, and the SFDR is increased to 77 dB. The SNDR of more than 60 dB and the SFDR of 74 dB can still be maintained at 4 times the Nyquist frequency (600M). The calibrated SHA-less structure ADC has a good intermediate frequency sampling performance. The entire calibration circuit consumes 3.1 mW at a 2.5 V analog voltage of 1.2 V digital voltage. The maximum sampling time deviation of this design can be calibrated to 250 ps, which is sufficient for pipelined ADCs for high-speed applications.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN792
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