【摘要】：隨著網(wǎng)絡(luò)技術(shù)和硬件制造技術(shù)的迅猛發(fā)展,系統(tǒng)間的數(shù)據(jù)傳輸量快速增加,導致傳輸接口的數(shù)據(jù)傳輸速率成為了阻礙系統(tǒng)性能提升的關(guān)鍵因素。并行傳輸技術(shù)抗干擾能力弱,易產(chǎn)生串擾、時鐘偏斜等現(xiàn)象,導致其數(shù)據(jù)傳輸速率難以提升。而串行傳輸技術(shù)可以有效解決這些問題使傳輸速率達到更高水平,再加上端口少、功耗低等優(yōu)點,串行鏈接技術(shù)(SerDes)受到越來越多的關(guān)注,逐漸成為數(shù)據(jù)傳輸?shù)闹髁骷夹g(shù)。本文通過對SerDes系統(tǒng)的研究,基于SMIC 0.13μm的CMOS工藝對SerDes接收端的信號丟失檢測電路和時鐘數(shù)據(jù)恢復電路進行了研究設(shè)計,并提出了一種抖動容限的仿真驗證方法。信號丟失檢測電路通過檢測輸入信號的差分擺幅值來濾除嚴重失真的信號和耦合到輸入端的噪聲。本文設(shè)計的信號丟失檢測電路的閾值電壓可以跟隨輸入信號的共模電平變化,使檢測結(jié)果不受輸入信號共模電平的影響。時鐘數(shù)據(jù)恢復電路采用相位插值的結(jié)構(gòu)設(shè)計,本文主要給出了相位跟蹤環(huán)路的電路設(shè)計,包括采樣電路、相位檢測電路、表決器、插值控制電路和相位插值電路。其中,相位檢測電路采用Bang-Bang型的半速率相位檢測器,采樣時鐘頻率不超過數(shù)據(jù)傳輸速率,提高了數(shù)據(jù)傳輸速率。相位插值的方法是先將全周期分為8個相位區(qū)間,然后在時鐘所在的相位區(qū)間內(nèi)對時鐘相位進行調(diào)節(jié)。該方法減小了插值步長,有利于準確調(diào)節(jié)時鐘相位。本文還提出了一種抖動容限的仿真驗證方法,通過VerilogA語言產(chǎn)生帶抖動的偽隨機數(shù)據(jù)作為測試信號,通過Python腳本判斷仿真輸出信號是否出錯。該方法在芯片設(shè)計階段對抖動容限進行仿真驗證,有效的降低了流片風險。抖動容限仿真結(jié)果表明,當抖動頻率在0.1MHz到10MHz之間時,抖動容限為0.61UI。在SerDes電路設(shè)計完成后,完成該芯片的版圖設(shè)計并將該芯片流片,然后對流片后的SerDse芯片進行測試。SerDes芯片的版圖面積為2363×2422μm。測試結(jié)果表明該芯片工作正確,數(shù)據(jù)傳輸速率可達到2.5Gbps。
[Abstract]:With the rapid development of the network technology and hardware manufacturing technology, the data transmission rate among the systems is rapidly increased, resulting in the data transmission rate of the transmission interface becoming the key factor to hinder the performance of the system. The anti-interference ability of parallel transmission technology is weak, it is easy to generate cross-talk, clock skew, and so on, which causes the data transmission rate to be difficult to increase. The serial transmission technology can effectively solve these problems, so that the transmission rate can reach a higher level, and the serial link technology (SerDes) is more and more concerned and gradually becomes the mainstream technology of data transmission. Based on the research of SerDes system, the signal loss detection circuit and clock data recovery circuit of SerDes receiving end are designed based on the CMOS process of the SMIC 0.13. m u.m, and a method of simulation and verification of the jitter tolerance is proposed. The signal loss detection circuit filters out the signal of the severe distortion and the noise coupled to the input terminal by detecting the differential swing amplitude of the input signal. The threshold voltage of the signal loss detection circuit designed in this paper can follow the common-mode level change of the input signal, so that the detection result is not affected by the common-mode level of the input signal. The clock data recovery circuit adopts the structure design of phase interpolation, and the circuit design of the phase tracking loop is mainly given in this paper, including the sampling circuit, the phase detection circuit, the voter, the interpolation control circuit and the phase interpolation circuit. The phase detection circuit adopts the half-rate phase detector of the Bang-Bang type, the sampling clock frequency does not exceed the data transmission rate, and the data transmission rate is improved. The phase interpolation method comprises the following steps of: firstly, dividing the full period into 8 phase sections, and then adjusting the clock phase in the phase section where the clock is located. The method reduces the interpolation step size and is beneficial to the accurate adjustment of the clock phase. In this paper, a simulation and verification method for jitter tolerance is presented, and the pseudo-random data with jitter is generated as a test signal through Verilog language, and the error of the simulation output signal is judged by the Python script. In that method, the jitter tolerance is simulated and verified at the design stage of the chip, and the risk of the flow sheet is effectively reduced. The jitter tolerance simulation results show that the jitter margin is 0.61 UI when the jitter frequency is between 0.1 MHz and 10 MHz. After the SerDes circuit design is completed, the layout of the chip is completed and the chip flow is completed, and then the SerDes chip after the convection chip is tested. The serial area of the SerDes chip is 2363-2422. m u.m. The test results show that the chip is working correctly and the data transmission rate can reach 2.5 Gbps.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN402

【參考文獻】

相關(guān)期刊論文 前7條

1 黃金鳳;王憶文;韋雪明;劉云龍;孫博文;;一種閾值自調(diào)整的高速串行信號丟失檢測電路[J];微電子學;2016年06期

2 邵剛;田澤;李世杰;呂俊盛;;一種高速SERDES抖動容限的高效仿真驗證方法[J];計算機技術(shù)與發(fā)展;2015年07期

3 李軒;張長春;李衛(wèi);郭宇鋒;張翼;方玉明;;2.5Gb/s PS/PI型半速率時鐘數(shù)據(jù)恢復電路設(shè)計[J];微電子學;2014年06期

4 潘敏;馮軍;楊婧;楊林成;;12.5Gb/s 0.18μm CMOS時鐘與數(shù)據(jù)恢復電路設(shè)計[J];電子學報;2014年08期

5 張長春;王志功;吳軍;郭宇峰;;5Gb/s0.18μm CMOS半速率時鐘與數(shù)據(jù)恢復電路設(shè)計[J];微電子學;2012年03期

6 林少衡;;一種帶信號丟失檢測告警功能的CMOS工藝限幅放大器[J];中國集成電路;2011年05期

7 王豪;黃啟俊;陶玉茂;蔣湘;周華;;具有閾值可編程信號檢測功能的BiCMOS限幅放大器[J];微電子學;2008年02期

相關(guān)會議論文 前1條

1 聶林川;鄧讓鈺;衣曉飛;;一種基于PI型CDR的相位檢測電路的實現(xiàn)與仿真[A];第十七屆計算機工程與工藝年會暨第三屆微處理器技術(shù)論壇論文集（下冊）[C];2013年

相關(guān)博士學位論文 前2條

1 韋雪明;高速SERDES接口芯片設(shè)計關(guān)鍵技術(shù)研究[D];電子科技大學;2012年

2 王東旅;高速串行通信中時間抖動的若干問題研究[D];中國科學技術(shù)大學;2011年

相關(guān)碩士學位論文 前10條

1 陳東旭;面向2.5G SerDes的8b/10b編解碼電路設(shè)計與測試[D];電子科技大學;2015年

2 陳超文;面向光纖通道的SerDes電路IP化技術(shù)研究[D];電子科技大學;2014年

3 李軒;2.5Gb/s PS/PI型半速率時鐘數(shù)據(jù)恢復電路的研究與設(shè)計[D];南京郵電大學;2014年

4 楊宗雄;2.5Gbps時鐘數(shù)據(jù)恢復電路的設(shè)計[D];電子科技大學;2012年

5 周祥福;高速VML收發(fā)器的研究與設(shè)計[D];電子科技大學;2011年

6 彭穎;SerDes芯片設(shè)計驗證及測試技術(shù)研究[D];電子科技大學;2011年

7 唐李紅;5Gbps高速串行接口電路的研究與設(shè)計[D];國防科學技術(shù)大學;2009年

8 王勇;高速時鐘數(shù)據(jù)恢復系統(tǒng)的研究[D];復旦大學;2009年

9 葉君青;用于1.25Gb/s千兆以太網(wǎng)的時鐘數(shù)據(jù)恢復電路的設(shè)計[D];上海交通大學;2008年

10 馮穎R，

本文編號：2496345