層次化物理設(shè)計中時序預(yù)算及優(yōu)化方法
發(fā)布時間：2019-03-23 17:04
【摘要】：在大規(guī)模、高頻率的芯片設(shè)計中,層次化設(shè)計的方法愈來愈普遍,而各個模塊的時序預(yù)算對時序的收斂有著重要的作用;隨著芯片尺寸的增大,片上誤差對于芯片的影響也愈發(fā)顯著;在高頻的設(shè)計中,時鐘偏差嚴重制約著芯片時序收斂的速度,而數(shù)據(jù)路徑上的延時成為影響時序收斂最重要的因素。本文基于40nm工藝下一款高性能多核DSP芯片YHFT-XX內(nèi)核的布局布線,針對其物理設(shè)計中制約時序收斂的關(guān)鍵問題做了相關(guān)研究,詳細闡述了使用的優(yōu)化方法。層次化物理設(shè)計中,各個模塊時序預(yù)算的合理程度影響著整個設(shè)計收斂的進度。本文對傳統(tǒng)的邊界最短化及依據(jù)邏輯深度的兩種時序預(yù)算方法進行了一定的分析,針對其不足之處,結(jié)合內(nèi)核設(shè)計的特點,提出了兩種新的時序預(yù)算方法:綜合考慮距離和邏輯深度的時序預(yù)算方法以及考慮時鐘的時序預(yù)算方法,并提出了對應(yīng)的預(yù)算公式。通過對公式的推演得出了時鐘上的偏差以及公共路徑對時序產(chǎn)生的影響。在時序預(yù)算的指導下,優(yōu)化了內(nèi)核的布圖規(guī)劃進行,使得關(guān)鍵路徑的長度減小了19.77%。降低片上誤差對芯片時序的影響越來越重要。本文通過對內(nèi)核時鐘結(jié)構(gòu)的詳細分析,結(jié)合各個子模塊時鐘的特點,對內(nèi)核的時鐘走向進行了細致的規(guī)劃,使得公共路徑比規(guī)劃前增加了5120um;在時鐘偏差方面,對于頂層復(fù)用模塊,通過分類的方法簡化了問題的復(fù)雜度,采用類H樹的方法優(yōu)化了時鐘延時和偏差,將復(fù)用模塊的偏差控制在15ps以內(nèi);對于邊界寄存器,通過嵌入調(diào)節(jié)點將其時鐘偏差減小至49ps,相對于工具自動運行的結(jié)果減小了39.5%,滿足了頂層的要求;對于硬宏及門控單元,將不同模塊中硬宏、門控單元的物理位置與多種時鐘結(jié)構(gòu)的特點相結(jié)合,對其時鐘進行規(guī)劃,并采取手工連線的方式優(yōu)化延時,它們之間的時鐘偏差均控制在10ps以內(nèi);而對于頂層分割出來的三個模塊,采取動態(tài)調(diào)節(jié)的方式來平衡時鐘偏差。本文通過對設(shè)計時鐘的規(guī)劃,解決了時鐘偏差給設(shè)計帶來的不利影響,為后期的時序優(yōu)化提供了保障。設(shè)計中數(shù)據(jù)通路的延時是制約設(shè)計收斂進度的難點。本文分析了關(guān)鍵路徑的特點,通過調(diào)節(jié)復(fù)位信號的起點,優(yōu)化了復(fù)位信號的保持時間,使其最大違反相比于優(yōu)化前減小了55.7%,總違反條數(shù)下降了68.7%,優(yōu)化效果相當顯著。對于超長的跨模塊數(shù)據(jù)通路,通過對關(guān)鍵站的寄存器進行手動布局,有效引導了數(shù)據(jù)流向,優(yōu)化了整個數(shù)據(jù)通路的延時。上述方法對YHFT-XX芯片設(shè)計中出現(xiàn)的問題效果明顯,最終實現(xiàn)了時序收斂,目前,該芯片已經(jīng)成功流片。
[Abstract]:In the large-scale, high-frequency chip design, hierarchical design method is becoming more and more popular, and the timing budget of each module plays an important role in timing convergence. With the increase of chip size, the effect of on-chip error on chip becomes more and more obvious. In the design of high frequency, clock deviation seriously restricts the speed of timing convergence, and the delay in the data path is the most important factor to influence the timing convergence. Based on the layout and routing of a high-performance multi-core DSP chip YHFT-XX kernel in 40nm process, the key problems restricting timing convergence in its physical design are studied in this paper, and the optimization methods used are described in detail. In hierarchical physical design, the timing budget of each module affects the convergence of the whole design. In this paper, the traditional boundary minimization and logical depth based on the two sequential budget methods are analyzed, aiming at its shortcomings, combined with the characteristics of kernel design, In this paper, two new timing budget methods are proposed: one is timing budget method considering distance and logical depth, the other is timing budget method considering clock, and the corresponding budget formula is put forward. The deviation on the clock and the effect of the common path on the timing are obtained through the derivation of the formula. Under the guidance of timing budget, the kernel layout planning is optimized and the critical path length is reduced by 19.77%. It is more and more important to reduce the influence of on-chip error on chip timing. Through the detailed analysis of the clock structure of the kernel, combined with the characteristics of each sub-module clock, the clock trend of the kernel is carefully planned, which makes the common path increase 5120umm compared with the pre-planning. In the aspect of clock deviation, for the top-level multiplexing module, the complexity of the problem is simplified by the classification method. The H-tree-like method is used to optimize the clock delay and deviation, and the deviation of the multiplexing module is controlled within the 15ps. For the boundary register, the clock deviation is reduced to 49 PS by embedding the adjustment node, and the result of automatic operation of the tool is reduced by 39.5%, which meets the requirement of the top level. For the hard macro and gate control unit, the physical position of the hard macro and gate control unit in different modules is combined with the characteristics of various clock structures, the clock is planned, and the delay is optimized by means of manual connection. The clock deviation between them is controlled within 10ps; For the top three modules, dynamic adjustment is adopted to balance the clock deviation. In this paper, the bad influence of clock deviation on the design is solved by planning the design clock, which provides a guarantee for the timing optimization in the later period. The delay of the data path in the design is a difficult point to restrict the convergence progress of the design. This paper analyzes the characteristics of the critical path. By adjusting the starting point of the reset signal, the holding time of the reset signal is optimized, so that the maximum violation of the reset signal is reduced by 55.7% compared with that before the optimization, and the total number of violations is decreased by 68.7%. The optimization effect is quite remarkable. For the ultra-long cross-module data path, the data flow is effectively guided and the delay of the whole data path is optimized by manually arranging the registers of the key station. The above-mentioned method has obvious effect on the design of YHFT-XX chip, and finally achieves timing convergence. At present, the chip has been successfully flowed.
【學位授予單位】：國防科學技術(shù)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402
本文編號：2446053
[Abstract]:In the large-scale, high-frequency chip design, hierarchical design method is becoming more and more popular, and the timing budget of each module plays an important role in timing convergence. With the increase of chip size, the effect of on-chip error on chip becomes more and more obvious. In the design of high frequency, clock deviation seriously restricts the speed of timing convergence, and the delay in the data path is the most important factor to influence the timing convergence. Based on the layout and routing of a high-performance multi-core DSP chip YHFT-XX kernel in 40nm process, the key problems restricting timing convergence in its physical design are studied in this paper, and the optimization methods used are described in detail. In hierarchical physical design, the timing budget of each module affects the convergence of the whole design. In this paper, the traditional boundary minimization and logical depth based on the two sequential budget methods are analyzed, aiming at its shortcomings, combined with the characteristics of kernel design, In this paper, two new timing budget methods are proposed: one is timing budget method considering distance and logical depth, the other is timing budget method considering clock, and the corresponding budget formula is put forward. The deviation on the clock and the effect of the common path on the timing are obtained through the derivation of the formula. Under the guidance of timing budget, the kernel layout planning is optimized and the critical path length is reduced by 19.77%. It is more and more important to reduce the influence of on-chip error on chip timing. Through the detailed analysis of the clock structure of the kernel, combined with the characteristics of each sub-module clock, the clock trend of the kernel is carefully planned, which makes the common path increase 5120umm compared with the pre-planning. In the aspect of clock deviation, for the top-level multiplexing module, the complexity of the problem is simplified by the classification method. The H-tree-like method is used to optimize the clock delay and deviation, and the deviation of the multiplexing module is controlled within the 15ps. For the boundary register, the clock deviation is reduced to 49 PS by embedding the adjustment node, and the result of automatic operation of the tool is reduced by 39.5%, which meets the requirement of the top level. For the hard macro and gate control unit, the physical position of the hard macro and gate control unit in different modules is combined with the characteristics of various clock structures, the clock is planned, and the delay is optimized by means of manual connection. The clock deviation between them is controlled within 10ps; For the top three modules, dynamic adjustment is adopted to balance the clock deviation. In this paper, the bad influence of clock deviation on the design is solved by planning the design clock, which provides a guarantee for the timing optimization in the later period. The delay of the data path in the design is a difficult point to restrict the convergence progress of the design. This paper analyzes the characteristics of the critical path. By adjusting the starting point of the reset signal, the holding time of the reset signal is optimized, so that the maximum violation of the reset signal is reduced by 55.7% compared with that before the optimization, and the total number of violations is decreased by 68.7%. The optimization effect is quite remarkable. For the ultra-long cross-module data path, the data flow is effectively guided and the delay of the whole data path is optimized by manually arranging the registers of the key station. The above-mentioned method has obvious effect on the design of YHFT-XX chip, and finally achieves timing convergence. At present, the chip has been successfully flowed.
【學位授予單位】：國防科學技術(shù)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402
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