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低功耗雙帶隙結構的CMOS帶隙基準源

發(fā)布時間:2019-01-29 00:44
【摘要】:隨著片上系統(tǒng)的發(fā)展,帶隙基準源精度和功耗的要求也越來越高.目前的高階溫度補償方法在工藝兼容、設計復雜度和功耗上還存在一定的局限性.本文推導了一個新穎的電流模帶隙基準電路在飽和區(qū)工作時的溫度特性,并結合雙帶隙結構在輸出支路上采用電流比例相減的方式實現(xiàn)有效的曲率補償,從而實現(xiàn)了一個新穎的雙帶隙結構CMOS帶隙基準源.在GSMC 0.18μm工藝下,設計的CMOS帶隙基準源版圖面積為0.066mm~2.蒙特卡羅后仿真的結果表明,在-40~125℃溫度范圍內平均溫度系數(shù)為14.27ppm/℃;在27℃時基準電壓平均值為1.201V,標準偏差變化僅為33.813mV(2.82%);在3.3V工作電壓下,靜態(tài)電流平均為9.865μA,電源抑制為-37.21dB.本文設計的帶隙基準源具有高精度、低功耗、結構簡單的特點,是片上系統(tǒng)的良好選擇.
[Abstract]:With the development of on-chip system, the precision and power consumption of bandgap reference are higher and higher. The current high-order temperature compensation methods have some limitations in process compatibility, design complexity and power consumption. In this paper, the temperature characteristics of a novel current-mode band-gap reference circuit operating in the saturation region are derived, and the effective curvature compensation is realized by using the current proportional subtraction method in the output branch combined with the dual-bandgap structure. A novel dual band gap CMOS bandgap reference source is realized. In the GSMC 0.18 渭 m process, the CMOS bandgap reference source layout area is 0.066 mm / 2. The results of Monte Carlo simulation show that the average temperature coefficient is 14.27ppm/ 鈩,

本文編號:2417472

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