【摘要】：紅外探測(cè)技術(shù)在如今的科學(xué)探測(cè)、軍事、醫(yī)療等方面的應(yīng)用越來(lái)越廣泛,對(duì)其性能的要求也日益提高。作為紅外探測(cè)系統(tǒng)中十分重要的一部分,紅外讀出電路的性能至關(guān)重要,其噪聲性能很大程度上決定了系統(tǒng)成像的質(zhì)量,因此設(shè)計(jì)低噪聲讀出電路有著十分重要的意義。本文設(shè)計(jì)了一款采用CDS技術(shù)的線列式紅外讀出電路。文中首先詳細(xì)分析了讀出電路中的MOS管噪聲、KTC噪聲和FPN噪聲,并在此基礎(chǔ)上重點(diǎn)分析了CDS技術(shù)對(duì)各類(lèi)噪聲的抑制效果。本紅外讀出電路的像素單元采用了CTIA結(jié)構(gòu)以穩(wěn)定探測(cè)器偏壓、抑制探測(cè)器噪聲以及提高輸出線性度。在列讀出級(jí)電路中,根據(jù)像素單元噪聲的特點(diǎn)針對(duì)性地設(shè)計(jì)了CDS電路,通過(guò)對(duì)CDS電路結(jié)構(gòu)以及工作時(shí)序的優(yōu)化,有效降低了列讀出級(jí)采樣電壓的噪聲。為了降低整體電路的功耗,列運(yùn)放采用了動(dòng)態(tài)尾電流供電的設(shè)計(jì)。此外,列運(yùn)放和輸出緩沖器都采用了噪聲較小的五管運(yùn)放結(jié)構(gòu)來(lái)降低電路的輸出噪聲。本文基于CSMC 0.5μm CMOS工藝完成了電路和版圖的設(shè)計(jì)與仿真。后仿真結(jié)果表明：電路能夠在5MHz的時(shí)鐘頻率下正常工作,輸出擺幅為3.0V,線性度為99.5%,單列電路的功耗為0.257mW,在保證以上指標(biāo)性能的同時(shí),輸出噪聲達(dá)到0.259mV,動(dòng)態(tài)范圍達(dá)到81.2dB,滿足設(shè)計(jì)指標(biāo)的要求。
[Abstract]:Infrared detection technology is more and more widely used in the fields of scientific detection, military affairs, medical treatment and so on. As a very important part of infrared detection system, the performance of infrared readout circuit is very important, and its noise performance determines the imaging quality of the system to a great extent, so it is very important to design low noise readout circuit. A linear infrared readout circuit using CDS technology is designed in this paper. In this paper, the noise of MOS tube, KTC noise and FPN noise in readout circuit are analyzed in detail, and the suppression effect of CDS technology on all kinds of noise is analyzed in detail. The pixel unit of the infrared readout circuit adopts CTIA structure to stabilize the detector bias, suppress the detector noise and improve the output linearity. In the column readout stage circuit, the CDS circuit is designed according to the characteristics of pixel cell noise. By optimizing the structure of the CDS circuit and the working sequence, the noise of the column readout stage sampling voltage is effectively reduced. In order to reduce the power consumption of the whole circuit, the dynamic tail current supply design is adopted. In addition, both the column operational amplifier and the output buffer adopt a five-tube amplifier structure with less noise to reduce the output noise of the circuit. The circuit and layout are designed and simulated based on CSMC 0. 5 渭 m CMOS process. The simulation results show that the circuit can work normally at the clock frequency of 5MHz, the output swing is 3.0V, the linearity is 99.5m and the power consumption of the single-row circuit is 0.257mW. at the same time, the performance of the above indexes is guaranteed. The output noise is 0.259 MV and the dynamic range is 81.2 dB, which meets the design requirements.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類(lèi)號(hào)】：TN215

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本文編號(hào)：2398996