基于FPGA的直接數(shù)字頻率合成器的設計
發(fā)布時間：2018-12-26 14:43
【摘要】：基于FPGA器件EP1K30QC208芯片,采用VHDL設計實現(xiàn)了一個相位、頻率均可控制的數(shù)字頻率合成器,并在ZY11EDA13BE試驗系統(tǒng)中完成硬件測試。經(jīng)實驗驗證,輸出波形達到了技術要求,性能良好,控制方便,證明了基于FPGA的DDS設計的可靠性和可行性。
[Abstract]:Based on the EP1K30QC208 chip of FPGA device, a digital frequency synthesizer with phase and frequency can be controlled by VHDL is designed and implemented, and the hardware is tested in the ZY11EDA13BE test system. The experimental results show that the output waveform meets the technical requirements, the performance is good and the control is convenient. The reliability and feasibility of the DDS design based on FPGA are proved.
【作者單位】： 巢湖學院;
【分類號】：TN74
[Abstract]:Based on the EP1K30QC208 chip of FPGA device, a digital frequency synthesizer with phase and frequency can be controlled by VHDL is designed and implemented, and the hardware is tested in the ZY11EDA13BE test system. The experimental results show that the output waveform meets the technical requirements, the performance is good and the control is convenient. The reliability and feasibility of the DDS design based on FPGA are proved.
【作者單位】： 巢湖學院;
【分類號】：TN74
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【共引文獻】
相關期刊論文 前10條
1 孫麗華,王磊R，
本文編號：2392268
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