超寬帶微波低噪聲放大器研究
發(fā)布時間：2018-11-17 20:53
【摘要】：現(xiàn)代的通訊系統(tǒng)隨著信息量的爆炸增長,對于帶寬,信息容量的要求與日俱增。超寬帶(UWB)無線通訊技術(shù)的出現(xiàn)能夠很好地解決上訴問題。而低噪聲放大器電路作為超寬帶接收機的前級電路,其性能關(guān)系著整體的帶寬,噪聲系數(shù),靈敏度,線性度等關(guān)鍵性指標。因此,設(shè)計在多倍頻程內(nèi)具有平坦增益的低噪聲放大器是實現(xiàn)超寬帶通訊系統(tǒng)的核心技術(shù)之一,具有重要的研究價值和廣闊的發(fā)展前景。與此同時,單片微波集成電路技術(shù)發(fā)展迅速,由于其具有小體積、良好的一致性、高穩(wěn)定性,批量成本低等特點,被廣泛應(yīng)用于最新低噪聲放大器電路的研制中。對比了四種不同的寬帶拓撲結(jié)構(gòu),結(jié)合設(shè)計帶寬要求,采用行波分布式結(jié)構(gòu)理論,對超寬帶匹配問題進行了研究,其核心思想是將晶體管的輸入輸出電容與級間電感結(jié)合構(gòu)成了柵極與漏極等效人工傳輸線,設(shè)計的人工傳輸線的等效特性阻抗等于端口阻抗,實現(xiàn)了超寬帶多倍頻程匹配。采用窄微帶線(帶狀電感器)實現(xiàn)所需電感,螺旋電感器寄生電容太大而不適用�；诜植际皆�,可知柵極,漏極線存在一定的損耗且隨頻率改變,結(jié)合晶體管的等效電路模型,MMIC工藝設(shè)計參數(shù)及分布式放大器原理,導(dǎo)出電路最優(yōu)節(jié)數(shù)optN的計算公式。傳統(tǒng)分布式放大器增益較低,所以采用共源共柵結(jié)構(gòu)代替共源結(jié)構(gòu),可以得到較低的柵-漏反饋電容和較高的輸出并聯(lián)電阻,使電路具有較寬的頻帶、較高的增益和較高的線性度。而這僅僅增加了少量的版圖面積。針對柵源電容遠大于漏源電容導(dǎo)致柵極線與漏極線相速不均衡的問題,在漏極傳輸線上串聯(lián)一個m衍生節(jié),可以有效得均衡相速,確保信號在漏極同相疊加輸出�；诜▏鳲MMIC 0.15?m GaAs pHEMT工藝加工制作了5級分布式放大器單片電路。測試的時候需要用到容值較大的離片電容元件作為去耦和低頻段擴展使用,將外置元件與芯片封裝成模塊。結(jié)果表明,芯片在0.5-18GHz增益大于10dB,不平坦度小于±1d B。輸入回波損耗小于-10dB,輸出回波損耗小于-12dB,帶內(nèi)噪聲系數(shù)平均3.5dB。芯片面積為1.8mm×1.2mm。
[Abstract]:With the explosion of information, modern communication systems require more and more bandwidth and information capacity. The emergence of UWB (UWB) wireless communication technology can solve the appeal problem well. As the front circuit of UWB receiver, the performance of low noise amplifier (LNA) is related to the bandwidth, noise coefficient, sensitivity, linearity and so on. Therefore, the design of low noise amplifier with flat gain in multiple frequency range is one of the core technologies to realize UWB communication system, which has important research value and broad development prospect. At the same time, monolithic microwave integrated circuit (MMIC) technology has been widely used in the development of the latest low noise amplifier circuits due to its small volume, good consistency, high stability, low batch cost and so on. In this paper, four different broadband topologies are compared, and the UWB matching problem is studied by using the theory of traveling wave distributed structure combined with the design bandwidth requirements. The core idea is to combine the input and output capacitance of the transistor with the inductance between stages to form a grid and drain equivalent artificial transmission line. The equivalent characteristic impedance of the designed artificial transmission line is equal to the port impedance, and the UWB multi-octave frequency path matching is realized. Narrow microstrip line (strip inductor) is used to realize the required inductance. The parasitic capacitance of spiral inductor is too large to be applicable. Based on the distributed principle, it is known that the grid and drain lines have certain losses and change with the frequency. Combining with the equivalent circuit model of transistors, the parameters of MMIC process design and the principle of distributed amplifiers, the formula for calculating the optimal section number of circuits optN is derived. The gain of traditional distributed amplifier is low, so the low gate leakage feedback capacitance and high output parallel resistance can be obtained by using the common source common-gate structure instead of the common source structure, so that the circuit has a wider frequency band. Higher gain and higher linearity. This adds only a small amount of territory. In order to solve the problem that the gate source capacitance is far larger than the drain source capacitance, the phase velocity of the grid line and the drain line is unbalanced. A m derivative section in series on the drain transmission line can effectively equalize the phase velocity and ensure the superposition of the signal at the drain pole in the same phase. A 5 stage distributed amplifier monolithic circuit is fabricated based on French OMMIC 0. 15 m GaAs pHEMT process. When testing, the off-chip capacitive elements with larger capacity are used as decoupling and low-frequency band expansion, and the external components and the chip are encapsulated into modules. The results show that the gain of 0.5-18GHz is greater than 10 dB and the unflatness is less than 鹵1 dB. The input echo loss is less than -10 dB, the output echo loss is less than -12 dB, and the average in-band noise coefficient is 3.5 dB. The chip area is 1.8mm 脳 1.2 mm.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN722.3
本文編號：2339008
[Abstract]:With the explosion of information, modern communication systems require more and more bandwidth and information capacity. The emergence of UWB (UWB) wireless communication technology can solve the appeal problem well. As the front circuit of UWB receiver, the performance of low noise amplifier (LNA) is related to the bandwidth, noise coefficient, sensitivity, linearity and so on. Therefore, the design of low noise amplifier with flat gain in multiple frequency range is one of the core technologies to realize UWB communication system, which has important research value and broad development prospect. At the same time, monolithic microwave integrated circuit (MMIC) technology has been widely used in the development of the latest low noise amplifier circuits due to its small volume, good consistency, high stability, low batch cost and so on. In this paper, four different broadband topologies are compared, and the UWB matching problem is studied by using the theory of traveling wave distributed structure combined with the design bandwidth requirements. The core idea is to combine the input and output capacitance of the transistor with the inductance between stages to form a grid and drain equivalent artificial transmission line. The equivalent characteristic impedance of the designed artificial transmission line is equal to the port impedance, and the UWB multi-octave frequency path matching is realized. Narrow microstrip line (strip inductor) is used to realize the required inductance. The parasitic capacitance of spiral inductor is too large to be applicable. Based on the distributed principle, it is known that the grid and drain lines have certain losses and change with the frequency. Combining with the equivalent circuit model of transistors, the parameters of MMIC process design and the principle of distributed amplifiers, the formula for calculating the optimal section number of circuits optN is derived. The gain of traditional distributed amplifier is low, so the low gate leakage feedback capacitance and high output parallel resistance can be obtained by using the common source common-gate structure instead of the common source structure, so that the circuit has a wider frequency band. Higher gain and higher linearity. This adds only a small amount of territory. In order to solve the problem that the gate source capacitance is far larger than the drain source capacitance, the phase velocity of the grid line and the drain line is unbalanced. A m derivative section in series on the drain transmission line can effectively equalize the phase velocity and ensure the superposition of the signal at the drain pole in the same phase. A 5 stage distributed amplifier monolithic circuit is fabricated based on French OMMIC 0. 15 m GaAs pHEMT process. When testing, the off-chip capacitive elements with larger capacity are used as decoupling and low-frequency band expansion, and the external components and the chip are encapsulated into modules. The results show that the gain of 0.5-18GHz is greater than 10 dB and the unflatness is less than 鹵1 dB. The input echo loss is less than -10 dB, the output echo loss is less than -12 dB, and the average in-band noise coefficient is 3.5 dB. The chip area is 1.8mm 脳 1.2 mm.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN722.3
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