低功耗高速時鐘數(shù)據(jù)恢復(fù)電路
發(fā)布時間：2018-10-23 08:34
【摘要】：為了降低高速串行接口的時鐘數(shù)據(jù)恢復(fù)(CDR)電路的功耗,在研究、分析現(xiàn)有時鐘數(shù)據(jù)恢復(fù)結(jié)構(gòu)的基礎(chǔ)上,提出了一種新的時鐘數(shù)據(jù)鑒相算法及其電路實現(xiàn)方法。新的電路設(shè)計僅使用一個高速采樣時鐘,比傳統(tǒng)的鑒相電路減少一半的采樣率,從而減少了前端采樣模塊的功耗。該鑒相算法采用統(tǒng)計方法減小鑒相時鐘的噪聲,進而達到很低的誤碼率。該鑒相算法可使用數(shù)字綜合的方法實現(xiàn),工作在較低的頻率下,這樣便于遷移到不同的工藝中。整個電路使用40nm工藝實現(xiàn),實際芯片測試數(shù)據(jù)表明,使用該電路的接收端可以穩(wěn)定工作在13Gb/s的速率下,功耗達到0.83p J/bit,誤碼率低于10E-12。
[Abstract]:In order to reduce the power consumption of the clock data recovery (CDR) circuit with high speed serial interface, a new clock data phase detection algorithm and its implementation method are proposed based on the analysis of the existing clock data recovery structure. The new circuit design uses only one high-speed sampling clock, which reduces the sampling rate by half compared with the traditional phase detection circuit, thus reducing the power consumption of the front-end sampling module. The phase detection algorithm uses statistical method to reduce the noise of phase detection clock and achieve a very low bit error rate (BER). The phase detection algorithm can be realized by digital synthesis, working at low frequency, which is easy to migrate to different processes. The whole circuit is implemented in 40nm technology. The actual chip test data show that the receiver using this circuit can work stably at the rate of 13Gb/s, and the power consumption is 0.83p / J / bit. the bit error rate is lower than 10E-12.
【作者單位】： 計算機體系結(jié)構(gòu)國家重點實驗室(中國科學院計算技術(shù)研究所);中國科學院計算技術(shù)研究所;中國科學院大學;
【基金】：國家“核高基”科技重大專項課題(2009ZX01028-002-003,2009ZX01029-001-003,2010ZX01036-001-002,2012ZX01029-001-002-002,2014ZX01020201,2014ZX01030101) 國家自然科學基金(61521092,61133004,61173001,61232009,61222204,61432016) 863計劃(2013AA014301)資助項目
【分類號】：TN402
[Abstract]:In order to reduce the power consumption of the clock data recovery (CDR) circuit with high speed serial interface, a new clock data phase detection algorithm and its implementation method are proposed based on the analysis of the existing clock data recovery structure. The new circuit design uses only one high-speed sampling clock, which reduces the sampling rate by half compared with the traditional phase detection circuit, thus reducing the power consumption of the front-end sampling module. The phase detection algorithm uses statistical method to reduce the noise of phase detection clock and achieve a very low bit error rate (BER). The phase detection algorithm can be realized by digital synthesis, working at low frequency, which is easy to migrate to different processes. The whole circuit is implemented in 40nm technology. The actual chip test data show that the receiver using this circuit can work stably at the rate of 13Gb/s, and the power consumption is 0.83p / J / bit. the bit error rate is lower than 10E-12.
【作者單位】： 計算機體系結(jié)構(gòu)國家重點實驗室(中國科學院計算技術(shù)研究所);中國科學院計算技術(shù)研究所;中國科學院大學;
【基金】：國家“核高基”科技重大專項課題(2009ZX01028-002-003,2009ZX01029-001-003,2010ZX01036-001-002,2012ZX01029-001-002-002,2014ZX01020201,2014ZX01030101) 國家自然科學基金(61521092,61133004,61173001,61232009,61222204,61432016) 863計劃(2013AA014301)資助項目
【分類號】：TN402
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4 邱e麠，
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