【摘要】：性能和功耗是評(píng)價(jià)一款芯片優(yōu)良的重要指標(biāo)。隨著芯片的集成度越來(lái)越高,工藝的特征尺寸越來(lái)越小,使得芯片設(shè)計(jì)的復(fù)雜程度成倍增長(zhǎng),導(dǎo)致芯片物理設(shè)計(jì)的工作壓力越來(lái)越大。同時(shí),電壓降、串?dāng)_、繞線、擁塞等因素對(duì)于芯片性能和功耗的影響越來(lái)越大,這些因素對(duì)芯片性能和功耗優(yōu)化工作提出了新的挑戰(zhàn)。本文對(duì)FT-DX芯片ALU部件的固化設(shè)計(jì)做了細(xì)致的研究,為了縮短設(shè)計(jì)周期,并且取得較好的時(shí)序結(jié)果,對(duì)ALU部件的物理設(shè)計(jì)采用了半定制設(shè)計(jì)方法,使用腳本結(jié)合EDA工具完成初步優(yōu)化,對(duì)其中的關(guān)鍵路徑和局部時(shí)鐘樹重構(gòu)做了手工的優(yōu)化。通過本文方法的優(yōu)化,ALU部件的時(shí)序結(jié)果與單純使用EDA工具進(jìn)行優(yōu)化的結(jié)果相比,時(shí)序優(yōu)化了31%,消除了97%的建立時(shí)間檢查違反路徑,迭代周期縮減了約50%。本文對(duì)掃描鏈在物理設(shè)計(jì)中的影響進(jìn)行了深入分析。為了減小掃描鏈路占用的布局資源,減小測(cè)試模式下掃描鏈路的時(shí)序違反和功耗,本文提出了一種結(jié)合掃描單元物理位置信息的掃描鏈定序方法。此方法通過減少掃描鏈路中插入的緩沖器數(shù)目和減少繞線,合理排列掃描單元連接順序,來(lái)達(dá)到降低掃描鏈路占用的布線資源,減少測(cè)試模式下掃描鏈路保持時(shí)間檢查違反和降低測(cè)試模式下掃描鏈路功耗的目的,并對(duì)傳統(tǒng)的物理設(shè)計(jì)流程進(jìn)行了改進(jìn)。結(jié)合FT-DX芯片的ALU部件,對(duì)本文方法進(jìn)行了實(shí)踐檢驗(yàn),結(jié)果證明,本文的掃描鏈定序方法與傳統(tǒng)方法相比,測(cè)試功耗降低了1.12%,總時(shí)序優(yōu)化了4.1%。本文提出了一種通過縮減非關(guān)鍵路徑上單元尺寸來(lái)降低功耗、減小保持時(shí)間檢查違反和布局資源的方法。通過結(jié)合Power Explorer工具,縮減非關(guān)鍵路徑上有優(yōu)化余量的單元的尺寸的方法,對(duì)傳統(tǒng)的物理設(shè)計(jì)優(yōu)化流程進(jìn)行了改進(jìn)。結(jié)合FT-DX芯片的ALU部件對(duì)本文提出的尺寸縮減方法進(jìn)行了實(shí)踐檢驗(yàn),結(jié)果證明本文提出的方法確實(shí)可以有效降低非關(guān)鍵路徑的功耗,比單純使用Power Explorer工具進(jìn)行功耗優(yōu)化所取得的好處增加了一倍。
[Abstract]:Performance and power consumption are important indexes to evaluate a chip. With the increasing integration of the chip, the characteristic size of the process becomes smaller and smaller, which makes the complexity of the chip design increase exponentially, resulting in the working pressure of the chip physical design is increasing. At the same time, voltage drop, crosstalk, wire winding, congestion and other factors have more and more influence on chip performance and power consumption. These factors pose a new challenge to chip performance and power optimization. In this paper, the solidification design of ALU parts of FT-DX chip is studied in detail. In order to shorten the design period and obtain better timing results, the semi-custom design method is used for the physical design of ALU parts. The script combined with EDA tool is used to optimize the critical path and local clock tree by hand. Through the optimization of the method in this paper, the timing results of ALU parts are optimized by 31%, 97% of the setup time is eliminated, and the iteration period is reduced by about 50% compared with the results of simple optimization using EDA tools. In this paper, the influence of scanning chain on physical design is analyzed. In order to reduce the layout resource occupied by the scanning link and to reduce the timing violation and power consumption of the scan link in test mode, a scanning chain ordering method combining the physical location information of the scanning unit is proposed in this paper. By reducing the number of buffers inserted in the scanning link, reducing the winding and arranging the connection order of the scanning unit reasonably, the method can reduce the wiring resources occupied by the scanning link. The purpose of reducing scan link holding time in test mode to check violation and to reduce the power consumption of scan link in test mode is discussed, and the traditional physical design flow is improved. Combined with the ALU part of FT-DX chip, the method is tested. The results show that compared with the traditional method, the test power consumption is reduced by 1.12 and the total timing is optimized by 4.1. In this paper, we propose a method to reduce power consumption and hold time to check violations and layout resources by reducing cell size on non-critical paths. The traditional physical design optimization process is improved by using the Power Explorer tool to reduce the size of the unit with an optimization margin on the non-critical path. The size reduction method proposed in this paper is tested with the ALU part of FT-DX chip. The results show that the proposed method can effectively reduce the power consumption of non-critical path. The benefits of power optimization are more than double that of using Power Explorer tools alone.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402

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