基于納米工藝的高速自適應(yīng)均衡技術(shù)的研究與實(shí)現(xiàn)
發(fā)布時間：2018-10-21 19:23
【摘要】：當(dāng)今無線通信系統(tǒng)、光纖通信系統(tǒng)和背板傳輸系統(tǒng)等各類通信系統(tǒng)為人們提供了高質(zhì)量、高便捷的信息服務(wù),極大促進(jìn)了人們的生活和社會的發(fā)展。隨著通信技術(shù)的高速發(fā)展,由于信道的衰減、串?dāng)_以及反射等非理想因素,高速信號在傳輸過程中會發(fā)生失真的現(xiàn)象也越來越嚴(yán)重。均衡正是通過對信道傳輸特性進(jìn)行補(bǔ)償來處理碼間串?dāng)_(ISI)的一種技術(shù),其目的是提高信號完整性,降低系統(tǒng)誤碼率。然而,隨著信號速率的增加,高速均衡器尤其是自適應(yīng)高速均衡器的設(shè)計與實(shí)現(xiàn)面臨著嚴(yán)峻的挑戰(zhàn),需要在電路工作速度、補(bǔ)償能力、自適應(yīng)性以及面積和功耗等方面進(jìn)行優(yōu)化,并實(shí)現(xiàn)它們之間的良好折中,以滿足通信系統(tǒng)日益增長的技術(shù)要求。本文對高速串行通信中的自適應(yīng)均衡器的結(jié)構(gòu)進(jìn)行了研究,并在均衡結(jié)構(gòu)優(yōu)化的基礎(chǔ)上,采用CMOS工藝設(shè)計了多個應(yīng)用于接收端的高速均衡器并進(jìn)行了流片和驗(yàn)證。本文首先從頻域和時域的角度分析了高速背板信道的的損耗、串?dāng)_、反射及噪聲等非理想特性對信號傳輸?shù)挠绊�。�?jù)此結(jié)合已有的主流均衡技術(shù)及其適應(yīng)條件,基于ADS仿真平臺對典型的背板信道進(jìn)行了仿真,通過分析比較,綜合考慮面積、功耗和可行性等因素,選取優(yōu)化的線性均衡器(LE)和判決反饋均衡器(DFE)組合方案,為后續(xù)均衡器結(jié)構(gòu)與電路的研究設(shè)計打下了基礎(chǔ)。根據(jù)仿真得到的組合均衡器結(jié)構(gòu),本文設(shè)計了用于接收端的高速前饋均衡器(FFE)+DFE組合均衡器。通過分析比較波特間隔均衡器(BSE)和分?jǐn)?shù)間隔均衡器(FSE)的特性,選取FSE結(jié)構(gòu)來減小頻譜混疊和采樣偏差的影響。針對傳統(tǒng)的DFE結(jié)構(gòu)很難滿足高速DFE設(shè)計要求的問題,本文采用半速率結(jié)構(gòu)以提高信號的傳輸速率和時鐘信號的準(zhǔn)確性。此外,在FFE電路的設(shè)計過程中,采用有源并聯(lián)電感峰化技術(shù)來增加延遲線帶寬。在此基礎(chǔ)上,本文基于TSMC 0.18μm CMOS工藝設(shè)計實(shí)現(xiàn)了FFE+DFE的高速均衡器,并進(jìn)行了流片和測試。測試結(jié)果顯示其在6.25Gb/s的傳輸速率下均衡輸出眼圖的水平張開度達(dá)到0.84UI,可以很好地補(bǔ)償信道在6.25GHz處達(dá)22dB的衰減。在成功設(shè)計了高速FFE+DFE組合均衡器的基礎(chǔ)上,本文進(jìn)一步研究并設(shè)計了一個10Gb/s連續(xù)時間線性均衡器(CTLE)+DFE組合均衡器,解決了由于FFE的帶寬受工藝截止頻率的限制以及延遲電路對工藝偏差敏感所導(dǎo)致的組合均衡器工作速度受限的問題。通過分析比較無源RLC濾波器和有源差分濾波器兩種結(jié)構(gòu)的特點(diǎn),設(shè)計了基于有源差分濾波器的CTLE,并在電路中引入了調(diào)諧功能,使CTLE能夠有效地對信道進(jìn)行補(bǔ)償。本文基于TSMC 0.18μmmCMOS工藝設(shè)計實(shí)現(xiàn)的CTLE+DFE組合均衡器已成功流片并進(jìn)行了測試,測試結(jié)果顯示在10Gb/s的傳輸速率下均衡輸出眼圖的水平張開度達(dá)到0.63UI,對在10GHz處衰減達(dá)3 1dB的信道有很好的均衡作用。在對組合均衡器的結(jié)構(gòu)和電路以及其自適應(yīng)實(shí)現(xiàn)方式充分研究的基礎(chǔ)上,本文采用IBM 0.13μmBiCMOS工藝設(shè)計實(shí)現(xiàn)了20Gb/s+的CTLE+DFE的自適應(yīng)均衡器。其中,CTLE采用基于斜率比較的自適應(yīng)結(jié)構(gòu),并對電路進(jìn)行了優(yōu)化,減小了電路的面積和功耗。DFE中抽頭系數(shù)的更新則采用模擬LMS算法電路,實(shí)現(xiàn)了速度和性能的良好折中。同時,為了滿足20Gb/s及以上信號速率的時序要求,DFE的主體結(jié)構(gòu)采用半速率預(yù)處理結(jié)構(gòu)以降低反饋路徑的延遲時間。本文的最后給出了所設(shè)計的自適應(yīng)均衡器的芯片照片和測試結(jié)果,整個芯片包括焊盤在內(nèi)的芯片面積為0.78×O.8mm2。測試結(jié)果表明當(dāng)速率為20Gb/s的信號經(jīng)過20GHz處的衰減達(dá)20dB,反射達(dá)13dB的背板信道時,信道末端的眼圖早已完全閉合,經(jīng)過自適應(yīng)均衡器后,輸出眼圖的水平張開度達(dá)到了0.85UI。該均衡器最高可工作在24Gb/s的速率上,對應(yīng)的輸出眼圖張開度為0.81UI。在3.3V的電源電壓下,功耗為624mW。目前國內(nèi)在高速均衡器設(shè)計與實(shí)現(xiàn)方面與國際上仍有一定差距,本文的工作不僅能夠推動相關(guān)領(lǐng)域的研究進(jìn)一步向前發(fā)展,具有重要的學(xué)術(shù)價值,而且對我國高速集成電路的設(shè)計也具有重要的應(yīng)用價值。
[Abstract]:Nowadays, various communication systems, such as wireless communication system, optical fiber communication system and backplane transmission system, provide high-quality and convenient information service for people, which greatly promotes the development of people's life and society. With the rapid development of communication technology, the distortion of high-speed signal in transmission process is becoming more and more serious due to non-ideal factors such as fading, crosstalk and reflection. equalization is a technique to deal with inter-code crosstalk (isi) by compensating channel transmission characteristics with the aim of improving signal integrity and reducing system error rate. However, as the signal rate increases, the design and implementation of high-speed equalizer, especially adaptive high-speed equalizer, faces severe challenges, and needs to be optimized in terms of circuit operating speed, compensation capacity, self-adaptability and area and power consumption, etc. and to achieve a good compromise between them to meet the increasing technical requirements of the communication system. In this paper, the structure of adaptive equalizer in high-speed serial communication is studied. Based on the optimization of the equalization structure, a plurality of high-speed equalizer applied to the receiving end is designed by CMOS process and the flow slice and verification are carried out. Firstly, the effects of non-ideal characteristics such as loss, crosstalk, reflection and noise on signal transmission are analyzed from the frequency domain and time domain. according to the existing mainstream equalization technology and the adaptation conditions, the typical backplane channel is simulated based on the ADS simulation platform, and the factors such as area, power consumption and feasibility are comprehensively considered through analysis and comparison, A combination of optimized linear equalizer (LE) and decision feedback equalizer (DFE) is chosen, which lays a foundation for the research and design of the following equalizer structure and circuit. In this paper, a high-speed feedforward equalizer (FFE) + DFE combined equalizer is designed for the receiving end according to the combined equalizer structure obtained by simulation. By analyzing the characteristics of the BSE and FSE, the FSE structure is selected to reduce the influence of frequency spectrum aliasing and sampling deviation. Aiming at the problem that the traditional DFE structure is difficult to meet the requirement of high-speed DFE design, the half-rate structure is adopted to improve the transmission rate of the signal and the accuracy of the clock signal. In addition, in the design process of FFE circuit, active parallel inductive peaking technology is used to increase the delay line bandwidth. On the basis of this, the high-speed equalizer of FFE + DFE is designed and implemented on the basis of TSMC 0. 18um CMOS process design, and the flow slice and test are carried out. The test results show that the horizontal opening degree of the equalized output signal at the transmission rate of 6,25Gb/ s reaches 0. 84UI, and the attenuation of 22dB at 6.25GHz can be well compensated. Based on the successful design of high speed FFE + DFE combined equalizer, a 10Gb/ s continuous time linear equalizer (CTLE) + DFE combined equalizer is further studied and designed. and solves the problem of limited working speed of the combined equalizer caused by the limitation of the cut-off frequency of the FFE and the sensitivity of the delay circuit to the process deviation. In this paper, the CTLE based on the active differential filter is designed and the tuning function is introduced in the circuit by analyzing the characteristics of the two structures of the non-source RLC filter and the active differential filter, so that the CTLE can effectively compensate the channel. The CTLE + DFE combined equalizer based on TSMC 0. 18. m CMOS process design has been successfully streamed and tested. The results show that the horizontal opening degree of the balanced output bridge at 10Gb/ s is 0.63UI, which has a good equalization effect on the channel with attenuation up to 31dB at 10GHz. Based on the full research on the structure and circuit of the combined equalizer and its adaptive implementation, the adaptive equalizer of 20Gb/ s + CTLE + DFE is designed in this paper. CTLE adopts self-adapting structure based on slope comparison, optimizes the circuit, reduces the area and power consumption of the circuit. The updating of tap coefficients in DFE uses an analog LMS algorithm circuit to achieve a good compromise between speed and performance. Meanwhile, in order to meet the timing requirement of 20Gb/ s and above signal rate, the main structure of DFE adopts half rate preprocessing structure to reduce the delay time of the feedback path. In the end of this paper, the chip photo and test result of the adaptive equalizer are presented. The chip area of the whole chip including the welding disc is 0.078 mmO. 8mm2. The test results show that when the signal rate of 20Gb/ s reaches 20dB at 20GHz and 13dB back plate channel is reflected, the horizontal opening of the end of the channel has been completely closed. After the adaptive equalizer, the horizontal opening degree of the output terminal reaches 0. 85UI. The equalizer can operate at a rate of 24Gb/ s, and the corresponding output value is 0. 81UI. At a power supply voltage of 3.3V, the power consumption is 624mW. At present, there are still some gaps in the design and implementation of high-speed equalizer in China. The work of this paper not only can promote further development of research in relevant fields, but also has important academic value, and also has important application value to the design of high-speed integrated circuit in China.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2015
【分類號】：TN715
本文編號：2286114
[Abstract]:Nowadays, various communication systems, such as wireless communication system, optical fiber communication system and backplane transmission system, provide high-quality and convenient information service for people, which greatly promotes the development of people's life and society. With the rapid development of communication technology, the distortion of high-speed signal in transmission process is becoming more and more serious due to non-ideal factors such as fading, crosstalk and reflection. equalization is a technique to deal with inter-code crosstalk (isi) by compensating channel transmission characteristics with the aim of improving signal integrity and reducing system error rate. However, as the signal rate increases, the design and implementation of high-speed equalizer, especially adaptive high-speed equalizer, faces severe challenges, and needs to be optimized in terms of circuit operating speed, compensation capacity, self-adaptability and area and power consumption, etc. and to achieve a good compromise between them to meet the increasing technical requirements of the communication system. In this paper, the structure of adaptive equalizer in high-speed serial communication is studied. Based on the optimization of the equalization structure, a plurality of high-speed equalizer applied to the receiving end is designed by CMOS process and the flow slice and verification are carried out. Firstly, the effects of non-ideal characteristics such as loss, crosstalk, reflection and noise on signal transmission are analyzed from the frequency domain and time domain. according to the existing mainstream equalization technology and the adaptation conditions, the typical backplane channel is simulated based on the ADS simulation platform, and the factors such as area, power consumption and feasibility are comprehensively considered through analysis and comparison, A combination of optimized linear equalizer (LE) and decision feedback equalizer (DFE) is chosen, which lays a foundation for the research and design of the following equalizer structure and circuit. In this paper, a high-speed feedforward equalizer (FFE) + DFE combined equalizer is designed for the receiving end according to the combined equalizer structure obtained by simulation. By analyzing the characteristics of the BSE and FSE, the FSE structure is selected to reduce the influence of frequency spectrum aliasing and sampling deviation. Aiming at the problem that the traditional DFE structure is difficult to meet the requirement of high-speed DFE design, the half-rate structure is adopted to improve the transmission rate of the signal and the accuracy of the clock signal. In addition, in the design process of FFE circuit, active parallel inductive peaking technology is used to increase the delay line bandwidth. On the basis of this, the high-speed equalizer of FFE + DFE is designed and implemented on the basis of TSMC 0. 18um CMOS process design, and the flow slice and test are carried out. The test results show that the horizontal opening degree of the equalized output signal at the transmission rate of 6,25Gb/ s reaches 0. 84UI, and the attenuation of 22dB at 6.25GHz can be well compensated. Based on the successful design of high speed FFE + DFE combined equalizer, a 10Gb/ s continuous time linear equalizer (CTLE) + DFE combined equalizer is further studied and designed. and solves the problem of limited working speed of the combined equalizer caused by the limitation of the cut-off frequency of the FFE and the sensitivity of the delay circuit to the process deviation. In this paper, the CTLE based on the active differential filter is designed and the tuning function is introduced in the circuit by analyzing the characteristics of the two structures of the non-source RLC filter and the active differential filter, so that the CTLE can effectively compensate the channel. The CTLE + DFE combined equalizer based on TSMC 0. 18. m CMOS process design has been successfully streamed and tested. The results show that the horizontal opening degree of the balanced output bridge at 10Gb/ s is 0.63UI, which has a good equalization effect on the channel with attenuation up to 31dB at 10GHz. Based on the full research on the structure and circuit of the combined equalizer and its adaptive implementation, the adaptive equalizer of 20Gb/ s + CTLE + DFE is designed in this paper. CTLE adopts self-adapting structure based on slope comparison, optimizes the circuit, reduces the area and power consumption of the circuit. The updating of tap coefficients in DFE uses an analog LMS algorithm circuit to achieve a good compromise between speed and performance. Meanwhile, in order to meet the timing requirement of 20Gb/ s and above signal rate, the main structure of DFE adopts half rate preprocessing structure to reduce the delay time of the feedback path. In the end of this paper, the chip photo and test result of the adaptive equalizer are presented. The chip area of the whole chip including the welding disc is 0.078 mmO. 8mm2. The test results show that when the signal rate of 20Gb/ s reaches 20dB at 20GHz and 13dB back plate channel is reflected, the horizontal opening of the end of the channel has been completely closed. After the adaptive equalizer, the horizontal opening degree of the output terminal reaches 0. 85UI. The equalizer can operate at a rate of 24Gb/ s, and the corresponding output value is 0. 81UI. At a power supply voltage of 3.3V, the power consumption is 624mW. At present, there are still some gaps in the design and implementation of high-speed equalizer in China. The work of this paper not only can promote further development of research in relevant fields, but also has important academic value, and also has important application value to the design of high-speed integrated circuit in China.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2015
【分類號】：TN715
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，本文編號：2286114
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