半導體器件與集成電路的ESD防護技術研究與實現(xiàn)
發(fā)布時間：2018-09-03 16:38
【摘要】：隨著半導體技術的不斷發(fā)展,人們對器件可靠性方面的研究也越來越深入,靜電放電對器件的危害得到了更多的重視。隨著對器件抗靜電能力要求的提高,一些符合原來標準要求的器件也需要提升其抗靜電能力。在此背景下,對以下內(nèi)容進行了分析和研究:1、對現(xiàn)有的一款JFET器件結構和實現(xiàn)流程進行了分析,并在TCAD軟件環(huán)境下編寫器件的仿真程序,建立了器件結構及雜質分布;2、對器件進行了基本參數(shù)仿真,在對比仿真結果與實際參數(shù)差別的基礎上,通過TCAD軟件仿真對現(xiàn)有器件的ESD能力進行了評估與分析,仿真結果表明:器件的ESD能力大于4KV;3、對ESD失效的器件樣品進行了分析,分別提出了器件接觸孔版圖的優(yōu)化設計,增加鎮(zhèn)流電阻使ESD電流分布更加均勻;對器件金屬層版圖設計規(guī)則進行調(diào)整,增大器件的源、漏金屬間距,提高器件兩極間的ESD電壓的承受能力;對器件的場氧化層工藝進行調(diào)整,增加源、漏兩極壓焊點下的介質層厚度,使器件在經(jīng)過粘接壓焊工藝后的抗ESD擊穿能力得到提高。最后實現(xiàn)了器件的ESD能力達到4KV以上;4、對器件的ESD測試方法進行了對比分析,針對器件成品ESD測試在時間以及成本上的不足,提出了一種在硅片上對器件進行ESD能力進行評估的簡易的晶圓級測試方法,并證明了這種測試方法在器件的研制階段可對各方案的ESD能力進行有效的評估。
[Abstract]:With the development of semiconductor technology, more and more research on the reliability of devices has been carried out, and the harm of electrostatic discharge to devices has been paid more attention. With the improvement of the antistatic ability of the devices, some devices that meet the requirements of the original standard also need to improve their antistatic ability. Under this background, the following contents are analyzed and studied: 1, the structure and implementation flow of an existing JFET device are analyzed, and the simulation program of the device is written under the environment of TCAD software. The device structure and impurity distribution are established, and the basic parameters of the device are simulated. On the basis of comparing the simulation results with the actual parameters, the ESD capability of the existing devices is evaluated and analyzed by TCAD software simulation. The simulation results show that the ESD capability of the device is more than 4KV ~ (3). The sample of ESD is analyzed, and the optimum design of the contact hole layout is put forward, and the distribution of ESD current is more uniform by increasing the ballast resistance. Adjust the layout rules of the metal layer of the device, increase the distance between the source and drain metal of the device, improve the withstand capacity of the ESD voltage between the two poles of the device, adjust the field oxidation layer process of the device, increase the source, The thickness of the dielectric layer under the pressure solder joint of the leakage two poles improves the ESD breakdown resistance of the device after the bonding process. Finally, the ESD capability of the device is up to more than 4% of 4KV. The ESD testing method of the device is compared and analyzed, aiming at the shortage of time and cost of the ESD test of the finished device. A simple wafer level test method is proposed to evaluate the ESD capability of the devices on silicon wafer. It is proved that this method can effectively evaluate the ESD capability of each scheme in the development stage of the device.
【學位授予單位】：北京工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TN305;O441.1;TN40
本文編號：2220555
[Abstract]:With the development of semiconductor technology, more and more research on the reliability of devices has been carried out, and the harm of electrostatic discharge to devices has been paid more attention. With the improvement of the antistatic ability of the devices, some devices that meet the requirements of the original standard also need to improve their antistatic ability. Under this background, the following contents are analyzed and studied: 1, the structure and implementation flow of an existing JFET device are analyzed, and the simulation program of the device is written under the environment of TCAD software. The device structure and impurity distribution are established, and the basic parameters of the device are simulated. On the basis of comparing the simulation results with the actual parameters, the ESD capability of the existing devices is evaluated and analyzed by TCAD software simulation. The simulation results show that the ESD capability of the device is more than 4KV ~ (3). The sample of ESD is analyzed, and the optimum design of the contact hole layout is put forward, and the distribution of ESD current is more uniform by increasing the ballast resistance. Adjust the layout rules of the metal layer of the device, increase the distance between the source and drain metal of the device, improve the withstand capacity of the ESD voltage between the two poles of the device, adjust the field oxidation layer process of the device, increase the source, The thickness of the dielectric layer under the pressure solder joint of the leakage two poles improves the ESD breakdown resistance of the device after the bonding process. Finally, the ESD capability of the device is up to more than 4% of 4KV. The ESD testing method of the device is compared and analyzed, aiming at the shortage of time and cost of the ESD test of the finished device. A simple wafer level test method is proposed to evaluate the ESD capability of the devices on silicon wafer. It is proved that this method can effectively evaluate the ESD capability of each scheme in the development stage of the device.
【學位授予單位】：北京工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2016
【分類號】：TN305;O441.1;TN40
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