【摘要】：現(xiàn)代電子技術的進步帶動了對高性能模數(shù)轉換器的需求。與其它結構模數(shù)轉換器相比,流水線ADC在速度、精度、功耗等方面具有獨特的優(yōu)勢,是近年來模數(shù)轉換器設計研究領域的重點之一。為進一步提高流水線ADC的性能,在傳統(tǒng)模擬電路設計因CMOS工藝進步而逐漸遭遇瓶頸的情況下,利用數(shù)字校準技術輔助模擬電路設計正成為流水線ADC研究與設計的趨勢。數(shù)字后臺校準技術可以在不打斷流水線ADC正常轉換工作的情況下,及時動態(tài)地校準流水線ADC的誤差,提高流水線ADC的性能指標。本文基于8位流水線ADC設計,分析了各類影響流水線ADC性能的誤差參數(shù),并針對最為重要的電容失配與運放有限增益引起的誤差,提出了一種數(shù)字后臺校準方案。該方案通過向被校準流水線級的MDAC電路注入PN序列,計算由上述兩者引起的級間增益誤差,修正該級數(shù)字量輸出,以此來校準流水線ADC的線性及非線性誤差,并通過反饋補償?shù)姆绞降窒艘隤N序列帶來的額外影響。該方案經(jīng)過Simulink建模驗證,仿真結果表明,應用校準方案后的流水線ADC信噪失真比提高了 4dB,無雜散動態(tài)范圍提高了 21dB。經(jīng)驗證的校準方案最終通過數(shù)字集成電路實現(xiàn)。采用SMIC 0.18μm 1P6M工藝,完成了 RTL級代碼編寫、功能仿真、FPGA驗證、邏輯綜合、靜態(tài)時序分析、形式驗證、物理版圖設計及驗證等工作。最終得到的數(shù)字電路版圖工作頻率為25MHz,芯片面積約1.5*1.5mm2,功耗小于9mW。本文提出的數(shù)字后臺校準方案,達到了校準流水線ADC電容失配與運放有限增益誤差的效果,提升了流水線ADC的性能指標。其電路實現(xiàn)面積小、功耗低,具有實際意義。
[Abstract]:The development of modern electronic technology drives the demand for high performance A / D converters. Compared with other analog-to-digital converters, pipelined ADC has unique advantages in speed, precision, power consumption and so on. It is one of the most important research fields in the design of analog-to-digital converters in recent years. In order to further improve the performance of pipelined ADC, the traditional analog circuit design has gradually encountered a bottleneck due to the progress of CMOS process. The use of digital calibration technology to assist analog circuit design is becoming the trend of pipeline ADC research and design. The digital background calibration technique can dynamically calibrate the errors of pipelined ADC without interrupting the normal conversion of pipelined ADC and improve the performance of pipeline ADC. Based on the design of 8-bit pipelined ADC, this paper analyzes the error parameters that affect the performance of pipelined ADC, and proposes a digital background calibration scheme for the errors caused by the most important capacitive mismatch and limited gain of operational amplifier. By injecting PN sequence into the calibrated pipelined MDAC circuit, the scheme calculates the inter-stage gain error caused by the above two steps, and corrects the output of the digital output of the stage to calibrate the linear and nonlinear errors of the pipelined ADC. The additional effect of introducing PN sequence is offset by feedback compensation. The simulation results show that the signal-to-noise-to-noise ratio of pipelined ADC is increased by 4dBand the non-spurious dynamic range is increased by 21dB. the simulation results show that the proposed scheme is verified by Simulink modeling. The verified calibration scheme is finally implemented by digital integrated circuit. Using SMIC 0.18 渭 m 1P6M process, the work of RTL level code writing, functional simulation and verification, logic synthesis, static timing analysis, formal verification, physical layout design and verification are completed. The final digital circuit layout frequency is 25MHz, the chip area is about 1.5mm2, and the power consumption is less than 9mW. The digital background calibration scheme proposed in this paper achieves the effect of calibration pipeline ADC capacitor mismatch and limited gain error of operational amplifier and improves the performance index of pipeline ADC. The circuit has small area and low power consumption, which is of practical significance.
【學位授予單位】：北京交通大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN792

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