【摘要】：針對存在缺陷CMOL電路的單元容錯映射問題,提出了一種分級選擇電路門節(jié)點的容錯映射方法.首先通過拓撲排序求出電路門的邏輯級;然后采用級間隔的方式進行選擇,并對有缺陷連接的門節(jié)點進行懲罰,提高其被選擇配置的概率.實驗結果表明,與已有算法相比,該方法平均選擇配置的門節(jié)點總數(shù)明顯減少,在納米二極管常開缺陷密度為40%、犧牲0.18%線長的情況下,CPU平均運行時間減少了30.68%.
[Abstract]:In order to solve the problem of cell fault-tolerant mapping in CMOL circuits with defects, a fault tolerant mapping method for hierarchical selection of gate nodes is proposed. First, the logic level of the circuit gate is obtained by topological sorting, and then the gate node with defective connection is punished by the method of stage interval to increase its probability of being selected and configured. The experimental results show that compared with the existing algorithms, the average number of gate nodes selected in this method is significantly reduced, and the average CPU running time is reduced by 30.68 when the defect density of the nanodiodes is 40 and 0.18% line length is sacrificed.
【作者單位】： 寧波大學信息科學與工程學院;
【基金】：國家自然科學基金(61571248,61501268) 浙江省自然科學基金(LQ15F040001) 寧波市自然科學基金(2015A610112)
【分類號】：TN40
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本文編號：2182270