【摘要】：在半導(dǎo)體市場(chǎng)需求快速變化和行業(yè)競(jìng)爭(zhēng)白熱化的背景之下,縮短產(chǎn)品的加工周期、提高設(shè)備利用率和產(chǎn)品質(zhì)量,是企業(yè)保持盈利和較強(qiáng)市場(chǎng)競(jìng)爭(zhēng)力的重要手段。而要改善半導(dǎo)體生產(chǎn)線的性能,提高生產(chǎn)效益,需對(duì)半導(dǎo)體制造過程動(dòng)態(tài)調(diào)度的關(guān)鍵性能指標(biāo)進(jìn)行預(yù)測(cè)研究,通過分析性能指標(biāo)的影響因子,找到可調(diào)控的影響參數(shù)來實(shí)現(xiàn)優(yōu)化目標(biāo)。本課題主要針對(duì)加工周期、設(shè)備利用率以及成品率這三個(gè)關(guān)鍵性能指標(biāo)進(jìn)行研究,通過建立多性能指標(biāo)同步預(yù)測(cè)模型來實(shí)現(xiàn)對(duì)加工周期和設(shè)備利用率的同步預(yù)測(cè)及分析,利用半導(dǎo)體生產(chǎn)線獲取的晶圓缺陷數(shù)據(jù)來完成晶圓缺陷聚集特性分析和對(duì)成品率的預(yù)測(cè)研究。本文圍繞半導(dǎo)體制造過程動(dòng)態(tài)調(diào)度的關(guān)鍵參數(shù)預(yù)測(cè)模型開展了如下的研究：1、針對(duì)半導(dǎo)體生產(chǎn)線動(dòng)態(tài)環(huán)境下的加工周期和設(shè)備利用率的預(yù)測(cè)問題,研究一種基于貝葉斯神經(jīng)網(wǎng)絡(luò)的多性能指標(biāo)同步預(yù)測(cè)模型,并構(gòu)建了一種閉環(huán)修正模型結(jié)構(gòu)。此外,利用貝葉斯神經(jīng)網(wǎng)絡(luò)可根據(jù)輸入對(duì)輸出的重要性來調(diào)整網(wǎng)絡(luò)權(quán)值的特性,設(shè)計(jì)一種權(quán)值分析法,來識(shí)別加工周期和設(shè)備利用率的關(guān)鍵影響因子。2、針對(duì)晶圓缺陷問題,研究一種缺陷數(shù)據(jù)驅(qū)動(dòng)的半導(dǎo)體成品率預(yù)測(cè)方法,利用基于密度的聚類方法對(duì)晶圓缺陷聚集特性進(jìn)行分析,并給出一種模糊支持向量機(jī)方法來構(gòu)建成品率的預(yù)測(cè)模型。將本文提出的兩種預(yù)測(cè)模型應(yīng)用到半導(dǎo)體制造過程關(guān)鍵性能指標(biāo)的預(yù)測(cè)中,通過仿真結(jié)果和分析表明,這兩種預(yù)測(cè)模型能夠很好的實(shí)現(xiàn)對(duì)加工周期、設(shè)備利用率和成品率的預(yù)測(cè)和分析,為解決半導(dǎo)體制造過程動(dòng)態(tài)調(diào)度問題提供了指導(dǎo),為實(shí)現(xiàn)半導(dǎo)體生產(chǎn)線多目標(biāo)優(yōu)化奠定了基礎(chǔ)。
[Abstract]:Under the background of rapid change of semiconductor market demand and intense competition in the industry, shortening the processing cycle of products, improving the utilization rate of equipment and product quality is an important means for enterprises to maintain profitability and strong market competitiveness. In order to improve the performance and benefit of semiconductor production line, it is necessary to predict and study the key performance indexes of dynamic scheduling of semiconductor manufacturing process. Find adjustable impact parameters to achieve optimization goals. This paper mainly focuses on three key performance indexes, such as processing cycle, equipment utilization ratio and finished product rate, and realizes synchronous prediction and analysis of machining cycle and equipment utilization rate by establishing synchronous prediction model of multi-performance index. The wafer defect data obtained from semiconductor production line are used to analyze the aggregation characteristics of wafer defects and to predict the yield of wafer defects. In this paper, the key parameter prediction model of dynamic scheduling of semiconductor manufacturing process is studied as follows: 1. Aiming at the prediction of processing cycle and equipment utilization under the dynamic environment of semiconductor production line, A synchronization prediction model with multiple performance indexes based on Bayesian neural network is studied, and a closed loop modified model structure is constructed. In addition, according to the importance of input to output, Bayesian neural network is used to adjust the characteristics of network weights, and a weight analysis method is designed to identify the key influencing factors of processing cycle and equipment utilization. In this paper, a defect data-driven method for predicting the yield of semiconductor products is studied. The density based clustering method is used to analyze the aggregation characteristics of wafer defects, and a fuzzy support vector machine (FSVM) method is proposed to build a prediction model of the yield. The two prediction models proposed in this paper are applied to the prediction of the key performance indexes in semiconductor manufacturing process. The simulation results and analysis show that the two prediction models can realize the processing cycle well. The prediction and analysis of equipment utilization ratio and finished product rate provide guidance for solving the dynamic scheduling problem of semiconductor manufacturing process and lay a foundation for multi-objective optimization of semiconductor production line.
【學(xué)位授予單位】：北京化工大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN305

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 曹政才;趙會(huì)丹;吳啟迪;;基于自適應(yīng)神經(jīng)模糊推理系統(tǒng)的半導(dǎo)體生產(chǎn)線故障預(yù)測(cè)及維護(hù)調(diào)度[J];計(jì)算機(jī)集成制造系統(tǒng);2010年10期

相關(guān)碩士學(xué)位論文 前1條

1 朱丹丹;集成電路設(shè)計(jì)中針對(duì)隨機(jī)缺陷的成品率研究[D];大連理工大學(xué);2011年

，

本文編號(hào)：2156582