發(fā)布時(shí)間：2018-07-10 05:28

  本文選題：前導(dǎo)數(shù)字預(yù)測(cè) + 誤差修正邏輯��； 參考：《微電子學(xué)與計(jì)算機(jī)》2017年05期

【摘要】：對(duì)前導(dǎo)數(shù)字預(yù)測(cè)算法的誤差修正邏輯進(jìn)行分析改進(jìn)和設(shè)計(jì)實(shí)現(xiàn),重點(diǎn)對(duì)該誤差修正糾錯(cuò)模塊的邏輯設(shè)計(jì)進(jìn)行了分析證明,依據(jù)設(shè)計(jì)的邏輯表達(dá)式對(duì)其電路進(jìn)行了設(shè)計(jì).同時(shí)采用硬件描述語(yǔ)言VerilogHDL編程,結(jié)果使用QuartusⅡ進(jìn)行仿真驗(yàn)證.使用性能分析軟件對(duì)提出的糾錯(cuò)邏輯方案進(jìn)行驗(yàn)證,可以看出本糾錯(cuò)單元的電路在電路面積和功耗上都有明顯的改善.
[Abstract]:The error correction logic of the leading digit prediction algorithm is analyzed and implemented. The logic design of the error correction module is analyzed and proved, and the circuit is designed according to the designed logic expression. At the same time, the hardware description language Verilog HDL is used to program, and the results are verified by Quartus 鈪，

本文編號(hào)：2112242