本文選題：壓控振蕩器 + 相位噪聲��； 參考：《湖南大學》2015年碩士論文

【摘要】：隨著現代通信技術的日益發(fā)展,特別是無線通信技術的全面推廣,電子通信系統(tǒng)延續(xù)了高性能、低成本、集成化的發(fā)展趨勢,而壓控振蕩器又是無線通信技術最核心的部分,電子設備對壓控振蕩器的技術指標要求越來越高。傳統(tǒng)的分立壓控振蕩器功耗高、頻率范圍低且?guī)捳?與集成芯片之間的寄生參數大,這些都限制了它無法滿足現代無線的技術指標;而目前集成壓控振蕩器已經能夠集成,性能優(yōu)秀,但是與CMOS集成壓控振蕩器相比,有兩個明顯的不足:一是工藝成本高,如果整個系統(tǒng)都采用此類工藝(諸如砷化鎵工藝、雙極型工藝、Bi Cmos工藝),將使得產品的造價成倍的上升,難以實現批量生產;二是使用的不是CMOS工藝,與后端數字電路不兼容,也就難以進行系統(tǒng)級芯片設計(System On Chip)�，F在的客戶都追求小、精、廉的價值觀念,為了適應客戶的需求以及電子技術的主流發(fā)展趨勢,設計一款低相噪、寬頻域、低功耗的CMOS工藝的集成壓控振蕩器,易于進行系統(tǒng)級芯片設計,大幅提高整個產品的性能,使產品做到真正的物美價廉,已是電子通信技術發(fā)展的必然走向�；谠O計壓控振蕩器的基本理論,結合國內外的研究現狀,設計出了一款低相位噪聲、寬頻域CMOS集成壓控振蕩器。論文首先簡單的介紹了壓控振蕩器的發(fā)展狀況,并提出了相應的一些技術指標和要求,然后對集成壓控振蕩器的設計做出了分析,這些分析主要包括集成壓控振蕩器常用結構的特點、拓撲的選擇及LC振蕩器中變容管和片上電感的設計要求等等。論文重點介紹了低相位噪聲和寬頻域調諧的壓控振蕩器的設計,對平面螺旋電感進行了優(yōu)化和對MOS變容管進行了參數設計,通過建立壓控振蕩器的小信號等效模式,確立了設計參數。論文對壓控振蕩器的其他相關電路模塊也進行了簡單的分析。主要工作成果有:諧振回路無源器件的片上實現,對無源器件的閃爍噪聲進行重點優(yōu)化,降噪技術為二次諧波諧振技術和感性壓控端技術。電路設計采用SMIC 0.18μm CMOS射頻工藝,利用Cadence軟件的Spectre RF工具仿真,仿真結果為:中心頻率為2.00 GHz,輸出頻率為1.85 GHz到2.15 GHz,調諧范圍為15%,相位噪聲為-120 d Bc/@1MHz,靜態(tài)功耗為0.72 m W。完全達到了設計要求。
[Abstract]:With the development of modern communication technology, especially the popularization of wireless communication technology, electronic communication system continues the development trend of high performance, low cost and integration, and voltage controlled oscillator is the core part of wireless communication technology. The technical requirements of VCO are becoming higher and higher in electronic equipment. The traditional discrete voltage controlled oscillator has high power consumption, low frequency range and narrow bandwidth, and large parasitic parameters with the integrated chip, which limit it to meet the technical requirements of modern wireless, but the integrated voltage controlled oscillator has been able to integrate. Performance is excellent, but there are two obvious disadvantages compared to CMOS integrated VCO: one is the high cost of the process, if the whole system uses such a process (such as gallium arsenide process, Gallium arsenide process), The bipolar process (Bi CMOS process) will double the cost of the product and make it difficult to realize batch production. Second, it is difficult to design system on Chip because it is not a CMOS process and is incompatible with the back end digital circuit. In order to meet the needs of customers and the mainstream trend of electronic technology, we design an integrated VCO with low phase noise, wide frequency domain and low power consumption in CMOS process. It is an inevitable trend of the development of electronic communication technology that it is easy to design system-level chips, greatly improve the performance of the whole product, and make the products really good and cheap. Based on the basic theory of designing VCO, a low phase noise, broadband CMOS integrated VCO is designed. Firstly, the development of VCO is briefly introduced, and some technical specifications and requirements are put forward, then the design of integrated VCO is analyzed. These analyses mainly include the characteristics of the common structure of the integrated VCO, the choice of topology and the design requirements of the varactor and on-chip inductor in the LC oscillator. This paper mainly introduces the design of VCO with low phase noise and wide frequency domain tuning, optimizes the planar spiral inductor and designs the parameters of MOS varactor. The small signal equivalent mode of VCO is established. The design parameters are established. The other circuit modules of VCO are also analyzed in this paper. The main results are as follows: the on-chip realization of the passive devices in the resonant circuit, the optimization of the scintillation noise of the passive devices, the second harmonic resonance technology and the inductive voltage-controlled terminal technology are used to reduce the noise. The circuit is designed in SMIC 0.18 渭 m CMOS RF process. The simulation results are as follows: the center frequency is 2.00 GHz, the output frequency is 1.85 GHz to 2.15 GHz, the tuning range is 15x, the phase noise is -120 d Bc / r -1MHz, and the static power consumption is 0.72 MW. Fully meet the design requirements.
【學位授予單位】：湖南大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN752

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相關期刊論文 前2條

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本文編號：2108417