本文選題：現(xiàn)場總線 + 介質(zhì)結(jié)合單元　； 參考：《沈陽工業(yè)大學》2015年碩士論文

【摘要】：介質(zhì)結(jié)合單元（MAU）是總線供電的現(xiàn)場總線儀表中的接口電路，用于實現(xiàn)標準邏輯信號與傳輸介質(zhì)上的物理信號之間的轉(zhuǎn)換。MAU芯片是實現(xiàn)上述功能的大規(guī)�；旌闲盘柤呻娐�，目前只有少數(shù)國外公司可提供。MAU芯片的設計技術是現(xiàn)場總線儀表的核心技術之一，隨著現(xiàn)場總線技術的廣泛應用，MAU芯片的研制具有越來越重要的意義。 本文介紹了一種基于國內(nèi)工藝設計的MAU芯片，并重點討論了其中接收電路的設計和實現(xiàn)方法。設計采用了逆向與正向相結(jié)合的方法，首先對一種國外芯片進行了逆向分析，結(jié)合現(xiàn)場總線通信協(xié)議IEC61158-2中對信號傳輸質(zhì)量的要求，確定了電路結(jié)構(gòu)和各種性能指標，然后基于國內(nèi)工藝完成了設計。接收電路由開關電容濾波器和比較器兩個部分組成，主要功能是從總線上接收頻率范圍在7.8KHz-39KHz之間的信號并將其轉(zhuǎn)換為內(nèi)部數(shù)字電路所能識別的邏輯信號，同時抑制頻帶外的干擾及噪聲。 課題的技術難點在于將芯片原有的工藝替換為新工藝，需要對開關電容網(wǎng)絡的Z變換傳輸函數(shù)和比較器比較點的偏置電壓進行調(diào)整。另外原芯片的接收范圍為1KHz-44.3KHz，本文通過對電路的電容比進行優(yōu)化使接收范圍達到7.8KHz-40KHz，更加接近通信協(xié)議的要求。 首先使用Chiplogic Analyzer軟件提取電路、然后使用Cadence軟件整理功能模塊，，對各個模塊的功能進行分析，包括開關電容濾波器、比較器、運算放大器、偏置電路以及不交疊時鐘電路。開關電容濾波器是整個電路的關鍵部分，所以對于這部分進行了重點分析。在對整個電路分析之后，采用華虹NEC0.35um BCD工藝對電路進行工藝移植。利用仿真工具，對接收電路各個模塊以及整體功能進行仿真分析，結(jié)果達到現(xiàn)場總線通信協(xié)議IEC61158-2標準對接收電路的要求。最后完成電路的版圖設計并通過了DRC和LVS。
[Abstract]:The dielectric binding unit (mau) is the interface circuit in the fieldbus instrument which is powered by the bus. It is used to realize the conversion between the standard logic signal and the physical signal on the transmission medium. The mau chip is a large-scale mixed signal integrated circuit to realize the above functions. At present, only a few foreign companies can provide the design technology of .mau chip is one of the core technologies of fieldbus instrument. With the wide application of fieldbus technology, the development of mau chip is becoming more and more important. In this paper, a mau chip based on domestic process design is introduced, and the design and implementation of the receiving circuit are discussed in detail. The design adopts the method of combining reverse and forward. Firstly, the reverse analysis of a kind of foreign chip is carried out. According to the requirement of signal transmission quality in fieldbus communication protocol IEC61158-2, the circuit structure and various performance indexes are determined. Then the design is completed based on the domestic process. The receiving circuit consists of a switched capacitor filter and a comparator. The main function of the circuit is to receive the signal with the frequency range of 7.8 KHz-39KHz from the bus and convert it into a logical signal that can be recognized by the internal digital circuit. At the same time, the interference and noise outside the frequency band are suppressed. The technical difficulty lies in replacing the original process of the chip with the new process. It is necessary to adjust the Z transform transfer function of the switched capacitor network and the bias voltage of the comparator. In addition, the receiving range of the original chip is 1KHz-44.3KHz. by optimizing the capacitance ratio of the circuit, the receiving range reaches 7.8 KHz-40KHz, which is closer to the requirement of the communication protocol. Firstly, the circuit is extracted by Chiplogic Analyzer software, and then the function of each module is analyzed, including switched capacitor filter, comparator, operational amplifier, bias circuit and non-overlapping clock circuit. Switched-capacitor filter is the key part of the whole circuit, so this part is analyzed emphatically. After analyzing the whole circuit, the circuit is transplanted by Huahong NEC 0.35um BCD process. By using the simulation tool, each module and the whole function of the receiving circuit are simulated and analyzed. The results meet the requirements of the field bus communication protocol IEC61158-2 for the receiving circuit. Finally, the layout of the circuit is designed and passed through DRC and LVS.
【學位授予單位】：沈陽工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402

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