發(fā)布時(shí)間：2018-06-28 03:15

  本文選題：低功耗 + 近似計(jì)算��； 參考：《電子科技大學(xué)》2016年碩士論文

【摘要】：近年來,生物醫(yī)學(xué)設(shè)備、物聯(lián)網(wǎng)、可穿戴設(shè)備以及手機(jī)等便攜式設(shè)備的發(fā)展越來越快,越來越強(qiáng)大的處理功能,越來越快的運(yùn)行速度,不可避免的帶來了龐大的功耗。并且,隨著工藝線寬的不斷縮小,芯片的功率密度不斷上升,然而電池技術(shù)一直沒有突破性進(jìn)展,因此電池的續(xù)航能力成為了制約這些便攜式設(shè)備發(fā)展的一大重要原因。因此,低功耗技術(shù)的發(fā)展勢(shì)在必行。在數(shù)字信號(hào)處理方向,數(shù)字濾波器由于其各種優(yōu)點(diǎn)被廣泛應(yīng)用,其中FIR濾波器憑借其線性相位特性尤其受到青睞,并且常被應(yīng)用于如助聽器一類的醫(yī)療設(shè)備中。所以,研究FIR濾波器有非常廣闊的應(yīng)用前景。同時(shí),由于數(shù)字電路一般都是根據(jù)最差情況設(shè)計(jì)的,然而這種最差情況極少出現(xiàn),所以勢(shì)必會(huì)造成資源浪費(fèi)。因此,可以通過犧牲一部分結(jié)果精確度的辦法來降低資源消耗,這就是近似計(jì)算理論。近似計(jì)算理論最早應(yīng)用于計(jì)算機(jī)系統(tǒng)中,而后憑借其優(yōu)秀的效果被廣泛應(yīng)用于各個(gè)領(lǐng)域。本文基于近似計(jì)算理論,在硬件、功耗等資源消耗與運(yùn)算結(jié)果精確度之間進(jìn)行權(quán)衡,設(shè)計(jì)了一種低功耗數(shù)字FIR濾波器。首先,本文介紹了半導(dǎo)體集成電路的發(fā)展趨勢(shì)和現(xiàn)在所面臨的困難,闡述了研究低功耗技術(shù)的價(jià)值,并對(duì)數(shù)字信號(hào)處理系統(tǒng)的發(fā)展作了介紹,分析了設(shè)計(jì)數(shù)字濾波器的意義。其次,本文介紹了數(shù)字電路功耗的組成部分,產(chǎn)生原因以及計(jì)算方式,從設(shè)計(jì)層次入手介紹了一些低功耗技術(shù)方法,并且介紹了數(shù)字濾波器的基礎(chǔ)理論與近似計(jì)算理論。之后,本文研究了數(shù)字電路中非常常用的乘法器,設(shè)計(jì)了一種非常適用于數(shù)字濾波器的,補(bǔ)償電路簡(jiǎn)單并且誤差較小的基于CSD編碼的截位補(bǔ)償乘法器,在保持性能不變的情況下,可以降低50%的功耗。然后,本文設(shè)計(jì)了一種基于近似計(jì)算理論的,濾波器階數(shù)與系數(shù)動(dòng)態(tài)可調(diào)的低功耗數(shù)字FIR濾波器,并且進(jìn)行了后端設(shè)計(jì)與仿真分析,驗(yàn)證了本文所設(shè)計(jì)低功耗數(shù)字濾波器功能正確,并且能夠在犧牲一部分計(jì)算精度的情況下,大幅度降低功耗,最多可以降低大約70%的功耗。本文所設(shè)計(jì)的低功耗數(shù)字濾波器采用的是0.13μm標(biāo)準(zhǔn)CMOS工藝進(jìn)行的設(shè)計(jì)及仿真分析。
[Abstract]:In recent years, the development of biomedical devices, Internet of things, wearable devices, mobile phones and other portable devices is becoming more and more rapid, more and more powerful processing functions, faster and faster running speed, which inevitably brings huge power consumption. With the continuous reduction of the process line width, the power density of the chip is increasing. However, there has been no breakthrough in battery technology, so the battery life ability has become an important factor restricting the development of these portable devices. Therefore, the development of low-power technology is imperative. In the direction of digital signal processing, digital filters are widely used because of their various advantages, among which Fir filters are particularly popular because of their linear phase characteristics, and are often used in medical devices such as hearing aids. Therefore, the study of Fir filter has a very broad application prospects. At the same time, because digital circuits are generally designed according to the worst case, however, this kind of worst-case rarely occurs, so it will lead to waste of resources. Therefore, resource consumption can be reduced by sacrificing some of the accuracy of results, which is called approximate computing theory. Approximate computing theory was first applied to computer systems, and then widely used in various fields by virtue of its excellent effect. Based on approximate computing theory, a low power digital Fir filter is designed based on the trade-off between hardware, power consumption and the accuracy of computing results. First of all, this paper introduces the development trend of semiconductor integrated circuit and the difficulties it faces now, expounds the value of studying low-power technology, introduces the development of digital signal processing system, and analyzes the significance of designing digital filter. Secondly, this paper introduces the components, causes and calculation methods of digital circuit power consumption, introduces some low-power technical methods from the design level, and introduces the basic theory and approximate calculation theory of digital filter. After that, this paper studies the multiplier which is very common in digital circuit, and designs a kind of truncated compensation multiplier based on CSD coding, which is very suitable for digital filter, which is simple in compensation circuit and small in error. The power consumption can be reduced by 50% while keeping the performance constant. Then, a low power digital Fir filter is designed based on approximate calculation theory, the order and coefficient of the filter are dynamically adjustable, and the back-end design and simulation analysis are carried out. It is verified that the low power digital filter designed in this paper is correct and can greatly reduce the power consumption by about 70% at the expense of some computational accuracy. The low power digital filter designed in this paper is based on 0.13 渭 m standard CMOS process.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN713.7

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