本文選題：SoC測(cè)試 + 低成本測(cè)試��； 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2015年博士論文

【摘要】：隨著集成電路與工藝技術(shù)的快速發(fā)展,片上系統(tǒng)(System-on-a-Chip, SoC)集成密度與復(fù)雜性不斷增長(zhǎng),嵌入芯核種類繁多,導(dǎo)致SoC芯片測(cè)試數(shù)據(jù)與測(cè)試功耗激增,而各芯核集成在SoC芯片內(nèi)部,無(wú)法通過(guò)外部I/O端口對(duì)其進(jìn)行直接訪問(wèn)與控制。同時(shí),SoC芯片集成規(guī)模不斷增加,而芯片管腳數(shù)有限,導(dǎo)致內(nèi)嵌芯核測(cè)試面臨難以控制和觀察等諸多難題,需要內(nèi)建可測(cè)性設(shè)計(jì)(Design for Testability,DFT)邏輯以提高其可控性和可觀性,這會(huì)引起SoC測(cè)試邏輯和測(cè)試時(shí)間開銷增高。過(guò)高的測(cè)試成本與測(cè)試功耗是SoC測(cè)試的兩大難題,因此,在SoC可測(cè)性設(shè)計(jì)中,研究低成本與低功耗測(cè)試技術(shù)成為該領(lǐng)域的熱點(diǎn)方向。本文以測(cè)試邏輯開銷、測(cè)試數(shù)據(jù)、測(cè)試應(yīng)用時(shí)間和測(cè)試功耗為優(yōu)化目標(biāo),分別在并發(fā)在線測(cè)試BIST結(jié)構(gòu)、測(cè)試數(shù)據(jù)編碼壓縮和掃描移位測(cè)試功耗等幾個(gè)方面開展SoC可測(cè)性設(shè)計(jì)中低成本與低功耗測(cè)試技術(shù)研究,主要研究成果和創(chuàng)新性包括以下幾點(diǎn)：1) 提出了一種基于多層解碼結(jié)構(gòu)改進(jìn)的并發(fā)在線測(cè)試BIST結(jié)構(gòu)及其低硬件開銷優(yōu)化方案。針對(duì)多層解碼邏輯結(jié)構(gòu)的實(shí)現(xiàn)特點(diǎn),研究并提出一種低硬件開銷優(yōu)化方案,包括輸入精簡(jiǎn)、解碼結(jié)構(gòu)改進(jìn)和模擬退火輸入重排序三種優(yōu)化算法。輸入精簡(jiǎn)用于合并確定性測(cè)試集中的相容列,精簡(jiǎn)需要解碼的輸入數(shù),以降低解碼開銷;通過(guò)將當(dāng)前解碼劃分后剩余不足本級(jí)分組列數(shù)一半的輸入直接傳輸至下一級(jí)解碼,改進(jìn)優(yōu)化分組以刪除部分冗余邏輯；而模擬退火輸入重排序?qū)Υ郎y(cè)電路的輸入進(jìn)行排序優(yōu)化,以降低解碼邏輯開銷。實(shí)驗(yàn)結(jié)果表明,優(yōu)化后解碼邏輯開銷在特定測(cè)試集與ATALANTA工具生成的測(cè)試集上可以分別平均降低20.96%和8.38%,測(cè)試成本得到有效降低。此外,對(duì)基于多層解碼邏輯的并發(fā)在線測(cè)試BIST結(jié)構(gòu)進(jìn)行改進(jìn),在輸出端同樣采用類似的多層解碼結(jié)構(gòu)對(duì)輸出響應(yīng)進(jìn)行解碼驗(yàn)證,使得改進(jìn)后的BIST結(jié)構(gòu)支持內(nèi)部邏輯不可見IP核的并發(fā)在線測(cè)試,適用范圍更廣2) 提出了兩種新的基于塊融合和相容性的測(cè)試數(shù)據(jù)編碼壓縮方案BMC和BM-8C。測(cè)試數(shù)據(jù)量與測(cè)試應(yīng)用時(shí)間是測(cè)試成本的兩個(gè)主要因素,本文分析了塊融合和9C編碼壓縮特點(diǎn),基于塊融合和相容性,對(duì)測(cè)試數(shù)據(jù)進(jìn)行塊劃分并融合連續(xù)相容數(shù)據(jù)塊后,在融合塊問(wèn)引入反相容、融合塊內(nèi)引入兩個(gè)半塊相容與反相容等特征構(gòu)造新的編碼測(cè)試壓縮方案BMC。實(shí)驗(yàn)結(jié)果表明,BMC編碼壓縮方案可以獲得平均高達(dá)68.02%的測(cè)試壓縮率,且相比于現(xiàn)有方案,測(cè)試應(yīng)用時(shí)間開銷可以平均降低9.37%。同時(shí),進(jìn)一步結(jié)合9C編碼壓縮特點(diǎn),引入融合塊內(nèi)各半塊能否能被全0或全1填充等特征進(jìn)行編碼壓縮構(gòu)造新的BM-8C編碼壓縮方案,以進(jìn)一步提升測(cè)試壓縮率并減少測(cè)試應(yīng)用時(shí)間。實(shí)驗(yàn)結(jié)果表明,BM-8C編碼壓縮方案可以平均獲得68.14%的測(cè)試壓縮率,且測(cè)試應(yīng)用時(shí)間開銷相對(duì)BMC方案平均減少0.73%,實(shí)現(xiàn)了低成本測(cè)試。此外BMC和BM-8C均為測(cè)試無(wú)關(guān)技術(shù),即其解壓縮電路與測(cè)試數(shù)據(jù)選取無(wú)關(guān),不需要隨著預(yù)先確定的測(cè)試集改變而進(jìn)行相應(yīng)修改。3)面向數(shù)據(jù)塊編碼壓縮方案,提出一種基于混合粒子群算法的塊內(nèi)重排序優(yōu)化技術(shù)。數(shù)據(jù)塊編碼壓縮效率很大程度上依賴于數(shù)據(jù)塊內(nèi)排序,不同的塊內(nèi)排序可能會(huì)導(dǎo)致同一測(cè)試數(shù)據(jù)塊具有不同編碼特征,從而對(duì)測(cè)試壓縮率產(chǎn)生影響。本文研究提出一種基于混合粒子群算法改進(jìn)的塊內(nèi)重排序優(yōu)化技術(shù),通過(guò)優(yōu)化數(shù)據(jù)塊內(nèi)排序,使得更多的數(shù)據(jù)塊具有可以被編碼壓縮成更短碼字的特征,從而減少測(cè)試數(shù)據(jù)存儲(chǔ)開銷,以提升測(cè)試壓縮率并降低測(cè)試應(yīng)用時(shí)間開銷。實(shí)驗(yàn)結(jié)果表明,經(jīng)塊內(nèi)重排序優(yōu)化后,BMC和BM-8C編碼壓縮方案可以分別獲得0.38%和0.43%的測(cè)試壓縮率提升,而測(cè)試應(yīng)用時(shí)間開銷分別下降0.82%和2.12%,且不會(huì)引入新的測(cè)試邏輯開銷。4) 基于掃描測(cè)試劃分,提出一種結(jié)合Q-D連接選擇性重構(gòu)策略和測(cè)試向量重排序算法的掃描移位測(cè)試功耗優(yōu)化方法。掃描測(cè)試劃分通過(guò)將掃描鏈劃分成等長(zhǎng)的多個(gè)掃描片段以降低測(cè)試數(shù)據(jù)掃描移位長(zhǎng)度,進(jìn)而減少掃描移位引起的掃描單元翻轉(zhuǎn)數(shù),可以有效降低掃描移位測(cè)試功耗。本文基于掃描測(cè)試劃分研究提出一種結(jié)合Q-D連接選擇性重構(gòu)策略和測(cè)試向量重排序算法的掃描移位測(cè)試功耗優(yōu)化方法,在各掃描鏈均勻劃分成多個(gè)掃描片段后,采用Q-D連接選擇性重構(gòu)各掃描片段內(nèi)相鄰掃描單元問(wèn)的連接方式,減少掃描移位操作引起的掃描單元冗余翻轉(zhuǎn)數(shù),并通過(guò)基于蟻群算法改進(jìn)的測(cè)試向量重排序算法優(yōu)化測(cè)試向量間排序,以降低相鄰測(cè)試向量間的跳變clash數(shù),進(jìn)一步降低掃描移位測(cè)試功耗。實(shí)驗(yàn)結(jié)果表明,掃描移位測(cè)試功耗經(jīng)優(yōu)化后在各掃描鏈劃分成4個(gè)和10個(gè)掃描片段下分別可以平均降低6.39%和7.64%,且提出的優(yōu)化方法不會(huì)對(duì)原有測(cè)試質(zhì)量、測(cè)試成本以及待測(cè)電路的性能造成影響,并適用于所有掃描測(cè)試結(jié)構(gòu)。
[Abstract]:With the rapid development of integrated circuits and technology, the integrated density and complexity of System-on-a-Chip (SoC) is increasing, and there are a wide variety of core cores, which results in a surge in testing data and test power of SoC chips, and core cores are integrated inside the SoC chip, and can not be directly accessed and controlled by the external I/O port. The size of SoC chip is increasing, and the number of chip pins is limited, which leads to the difficult control and observation of embedded core core testing. The Design for Testability (DFT) logic is needed to improve its controllability and observability. This will cause the higher cost of testing logic and test time of SoC and the high test cost. And test power consumption is the two difficult problem of SoC test. Therefore, in SoC testability design, the research of low cost and low power testing technology has become a hot topic in this field. This paper is based on test logic overhead, test data, test application time and test power consumption as the optimization target, and the BIST structure of concurrent on-line testing and test data coding compression respectively. The research of low cost and low power testing technology in SoC testability design is carried out in several aspects, such as scanning shift test power consumption. The main research results and innovation include the following points: 1) an optimization scheme for concurrent on-line test BIST based on multi-layer decoding structure and its low hardware cost optimization is proposed. A low hardware overhead optimization scheme is proposed, including three optimization algorithms for low hardware overhead, including input simplification, decoding structure improvement and simulated annealing input reordering. Input simplification is used to merge the compatible columns in a deterministic test set, streamline the input number needed to decode, and reduce the decoding overhead; by dividing the current decoding, it is divided after the current decoding. The input of half of the remaining sub class columns is transferred directly to the next level decoding, and the optimization packet is improved to delete partial redundant logic. The simulated annealing input reordering is used to sort the input of the test circuit to reduce the decoding logic overhead. The experimental results show that the decoding logic overhead is in a specific test set and ATALANT after the optimization. The test set generated by A tools can be reduced by 20.96% and 8.38% on average, and the cost of testing is reduced effectively. In addition, the BIST structure of concurrent online testing based on multi-layer decoding logic is improved. The output response is decode and validate the output response with similar multilayer decoding structure at the output end, making the improved BIST structure support inside. The Department logic can not see the concurrent online testing of IP kernel. The application scope is more wide 2) two new test data coding compression schemes based on block fusion and compatibility are proposed, BMC and BM-8C. test data amount and test application time are the two main factors of test cost. This paper analyzes block fusion and 9C coding compression characteristics, block fusion and block fusion. After block partition and fusion of continuous compatible data blocks for test data, a new coding test compression scheme is constructed in the fusion block to construct a new coding test compression scheme with 2.5 blocks of compatibility and anti compatibility in the fusion block. The results show that the BMC coding compression scheme can obtain an average of up to 68.02% of the test compression rate and phase of the BMC.. Compared with the existing scheme, the time overhead of test application can be reduced 9.37%. at the same time, and further combined with the features of 9C coding compression, a new BM-8C coding compression scheme can be constructed by introducing the features of all 0 or all 1 filling blocks in the fusion block, in order to further improve the test compression rate and reduce the test application time. The results show that the BM-8C coding compression scheme can obtain an average of 68.14% test compression rate, and the test application time cost is 0.73% less than the BMC scheme, and the BMC and BM-8C are all test independent techniques, that is, the decompression circuit is independent of the test data selection, and does not need to be changed with the pre determined test set. The corresponding modification.3) oriented data block coding and compression scheme, a kind of intra block reordering optimization technique based on Hybrid Particle Swarm Optimization (PSO) is proposed. The compression efficiency of data block coding is largely dependent on the sorting in the data block. The different block sorting may lead to the same test data block with different coding features, so that the test pressure can be tested. In this paper, an improved intra block reordering optimization technique based on Hybrid Particle Swarm Optimization (PSO) is proposed in this paper. By optimizing the data block sorting, more data blocks can be compressed into shorter codewords, thus reducing the test data storage opening, in order to improve the test compression rate and reduce the test application. The experimental results show that the BMC and BM-8C coding compression schemes can gain 0.38% and 0.43% test compression rates respectively after the block reordering optimization, while the test application time costs are reduced by 0.82% and 2.12% respectively, and the new test logic overhead is not introduced,.4) based on the scan test division, and a combination of Q-D connection selectivity is proposed. The scanning shift test power optimization method of the reconfiguration strategy and the test vector reordering algorithm. The scanning test division can reduce the scan shift length by dividing the scan chain into multiple scan segments to reduce the scan shift length of the test data, and reduce the scan shift unit turnover. This paper can effectively reduce the power consumption of the scan shift test. A scanning shift test power optimization method, which combines the Q-D connection selective reconfiguration strategy and the test vector reordering algorithm, is proposed. After the scan chain is divided into multiple scan segments, the Q-D connection is used to selectively reconstruct the connection mode of the adjacent scanning unit in the scanned segments and reduce the scan. In order to reduce the number of jump clash between adjacent test vectors and further reduce the power of scanning shift test, the experiment results show that the power of scanning shift test is optimized in each scan chain. The average reduction of 4 and 10 scanning segments can be reduced by 6.39% and 7.64% respectively, and the proposed optimization method will not affect the original test quality, the test cost and the performance of the circuit to be measured, and it is suitable for all the scanning test structures.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN407

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