本文選題：System + Verilog��； 參考：《西安電子科技大學(xué)》2015年碩士論文

【摘要】：隨著集成電路工藝與設(shè)計能力的不斷發(fā)展,SoC設(shè)計規(guī)模與復(fù)雜度持續(xù)增加。這使得SoC驗證工作的難度也日益增長,SoC的驗證工作已成為集成電路設(shè)計過程中的嚴(yán)峻挑戰(zhàn)。本論文針對驗證開展研究,在研究分析System Verilog驗證語言和通用驗證方法學(xué)(UVM)的基礎(chǔ)上,對SoC/IP的驗證特征與驗證需求進(jìn)行分析,根據(jù)SoC中IP模塊的相關(guān)協(xié)議規(guī)格搭建了驗證平臺,編寫了通用驗證組件。并根據(jù)驗證方法、通用驗證組件討論了如何將驗證平臺重用于其他IP模塊和系統(tǒng)級模塊等核心問題。在設(shè)計驗證階段,首先分析了SoC體系結(jié)構(gòu),提出驗證需求。利用UVM搭建驗證平臺。對于驗證平臺的結(jié)構(gòu),采用總線接口模型與抽象層次化結(jié)構(gòu)相結(jié)合的形式,為下一步SoC/IP驗證平臺的設(shè)計實現(xiàn)打下基礎(chǔ)。為保證驗證平臺具有可重用性的驗證需求,文中選取APB、UART總線接口模型作為通用組件,設(shè)計頂層控制模塊環(huán)境嵌套APB與UART通用組件子環(huán)境。在低層次組件中加入隨機(jī)約束、事務(wù)項、phase機(jī)制,實現(xiàn)驗證的隨機(jī)性、可控性。在驗證實施階段,根據(jù)UART設(shè)計模塊,分解覆蓋點(diǎn)采用隨機(jī)事務(wù)級激勵編寫測試項,在僅通過一條測試項的情況下,代碼覆蓋率與功能覆蓋率分別達(dá)到99.60%與100%,以此說明該驗證平臺有效提高了測試效率。仿真結(jié)束后自動生成執(zhí)行報告,記錄驗證環(huán)境運(yùn)行的驗證組件、寄存器配置信息,并通過UVM_INFO標(biāo)示transaction傳輸時正確與錯誤的信息。在探究驗證平臺可重用性階段,選取SPI待測模塊,運(yùn)用相同的驗證平臺。通過頂層控制模塊選取自定義的UART、APB驗證通用組件,從而配置生成適用于SPI的驗證環(huán)境,通過執(zhí)行測試項進(jìn)行仿真工作,收集代碼覆蓋率100%。以此說明對模塊級該驗證平臺的可重用性。再次選取APB子系統(tǒng),通過結(jié)構(gòu)圖闡述該驗證平臺進(jìn)行APB子系統(tǒng)級驗證所需通用組件的結(jié)構(gòu)與環(huán)境劃分。以此證明基于UVM可重用驗證平臺,對傳統(tǒng)驗證平臺在隨機(jī)性、可復(fù)用性、自動化等方面進(jìn)行了優(yōu)化,對集成化SoC驗證具有可行性。
[Abstract]:With the continuous development of IC technology and design capability, SoC design scale and complexity continue to increase. This makes the verification of SoC more and more difficult. The verification of SoC has become a severe challenge in the process of IC design. Based on the analysis of system Verilog verification language and universal verification methodology (UVM), the verification features and verification requirements of SoC / IP are analyzed, and the verification platform is built according to the protocol specifications of IP modules in SoC. A general verification component is written. According to the verification method, the common verification component discusses how to reapply the verification platform to other IP modules and system-level modules. In the phase of design and verification, the SoC architecture is analyzed and the verification requirements are put forward. UVM is used to build the verification platform. For the structure of the verification platform, the bus interface model and the abstract hierarchical structure are adopted to lay the foundation for the design and implementation of the next SoC / IP verification platform. In order to ensure the reusability of the verification platform, the API UART bus interface model is selected as the universal component, and the top-level control module environment is designed to nest APB and UART general component subenvironment. The randomness and controllability of verification are realized by adding random constraints and transaction item phase mechanism to the low level components. In the verification implementation phase, according to the UART design module, the decomposition coverage point uses random transaction-level incentives to write test items, and when only one test item is passed, The code coverage and function coverage are 99.60% and 100% respectively. At the end of the simulation, the execution report is generated automatically, the verification components running in the verification environment are recorded, the information of register configuration is recorded, and the correct and wrong information of transaction transmission is indicated by the transaction stack info. In the stage of exploring the reusability of verification platform, the SPI module is selected and the same verification platform is used. The self-defined UART APB is selected by the top-level control module to verify the universal components, so that the verification environment suitable for SPI is configured, the test items are executed to simulate, and the code coverage is 100%. This illustrates the reusability of the verification platform at the module level. The structure and environment partition of the general components needed for APB subsystem verification are illustrated by the structure diagram of APB subsystem. It is proved that based on UVM reusable verification platform, the traditional verification platform is optimized in randomness, reusability, automation and so on, which is feasible for integrated SoC verification.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

1 李洋洋;吳武臣;王龍偉;王寧;侯立剛;;基于斷言的驗證方法在UART模塊中的應(yīng)用研究[J];微電子學(xué)與計算機(jī);2010年01期

2 鐘文楓;;下一代芯片設(shè)計與驗證語言：SystemVerilog(驗證篇)[J];電子設(shè)計應(yīng)用;2008年12期

，

本文編號：2028644