發(fā)布時間：2018-06-12 03:55

  本文選題：薄膜晶體管 + D觸發(fā)器�。� 參考：《華南理工大學學報(自然科學版)》2017年03期

【摘要】：設計了一個基于Pseudo-CMOS邏輯門的低功耗異步復位D觸發(fā)器電路.該D觸發(fā)器全部由n型a-IGZO TFTs(薄膜晶體管)構成,采用動態(tài)負載替代Pseudo-CMOS拓撲中的二極管連接負載,通過減少電路導通的概率來降低靜態(tài)功耗.電路的輸出級為鎖存器,通過反饋通路減少由動態(tài)負載造成的輸出擺幅降低對延遲的影響.將該D觸發(fā)器應用于環(huán)行移位寄存器的設計中,結果表明,該觸發(fā)器電路可有效降低或非門邏輯電路中的靜態(tài)功耗.
[Abstract]:A low power asynchronous reset D flip-flop circuit based on Pseudo-CMOS logic gate is designed. The D-flip-flop consists of n-type a-IGZO TFTs (thin film transistor). The dynamic load is used to replace the diode connection load in Pseudo-CMOS topology, and the static power consumption is reduced by reducing the probability of circuit turn-on. The output stage of the circuit is a latch, and the effect of the output swing reduction caused by the dynamic load on the delay is reduced by the feedback path. The D flip-flop is applied to the design of the cyclic shift register. The results show that the flip-flop circuit can effectively reduce the static power consumption in the non-gate logic circuit.
【作者單位】： 華南理工大學電子與信息學院;
【基金】：國家自然科學基金資助項目(61274085) 廣東省科技計劃項目(2015B090909001)~~
【分類號】：TN783
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本文編號：2008225