本文選題：自組織網(wǎng) + 低延遲��； 參考：《電子科技大學(xué)》2015年碩士論文

【摘要】：不同于傳統(tǒng)有中心節(jié)點(diǎn)的基站-移動(dòng)終端模式的無線網(wǎng)絡(luò),無線自組織網(wǎng)是一種由若干個(gè)對(duì)等設(shè)備自由組成的無線網(wǎng)絡(luò)。由于其具有網(wǎng)絡(luò)結(jié)構(gòu)靈活、可獨(dú)立組網(wǎng)、抗毀性強(qiáng)等優(yōu)勢,無線自組織網(wǎng)已成為了無線通信技術(shù)發(fā)展的重要方向之一。無線自組織網(wǎng)通常采用CSMA/CA或TDMA的接入方式,其端到端傳輸時(shí)延較大,不適用于如軍事通信等對(duì)時(shí)延要求較高的場合。為解決自組織網(wǎng)中通信節(jié)點(diǎn)傳輸時(shí)延較大的問題,本文在以太網(wǎng)接口和物理層鏈路的基礎(chǔ)上,設(shè)計(jì)并在FPGA上實(shí)現(xiàn)了一種競爭和時(shí)分多址相結(jié)合的接入和組網(wǎng)方式,并實(shí)現(xiàn)了節(jié)點(diǎn)間的高精度全局時(shí)間同步。全文的主要工作如下:首先,討論了現(xiàn)有的自組織網(wǎng)接入方式以及常見的時(shí)間同步算法,并根據(jù)機(jī)載自組織網(wǎng)的時(shí)間同步及數(shù)據(jù)傳輸應(yīng)用場景,以及物理層鏈路和硬件系統(tǒng)的約束,提出了明確的低延遲自組織網(wǎng)的網(wǎng)絡(luò)層設(shè)計(jì)指標(biāo)。其次,根據(jù)設(shè)計(jì)指標(biāo),分為廣播通道、數(shù)據(jù)通道、收發(fā)切換三個(gè)大模塊設(shè)計(jì)了低延遲自組織網(wǎng)的網(wǎng)絡(luò)層方案,分別用于實(shí)現(xiàn)節(jié)點(diǎn)入退網(wǎng)及高精度時(shí)間同步、用戶IP化業(yè)務(wù)數(shù)據(jù)傳輸及TDD信道接入控制三大功能,并給出了一種在競爭接入模式和時(shí)分多址接入模式之間靈活切換的流程。隨后,分模塊詳細(xì)討論了廣播通道、數(shù)據(jù)通道和收發(fā)切換三大模塊的FPGA實(shí)現(xiàn)細(xì)節(jié),包括各大模塊的總體結(jié)構(gòu)框圖、各子模塊的狀態(tài)轉(zhuǎn)移、組幀與解幀的流程,以及競爭和時(shí)分多址接入模式的收發(fā)切換控制,并給出了一種通過以太網(wǎng)接口的UDP配置通道進(jìn)行鏈路管理的方法。最后,本文對(duì)網(wǎng)絡(luò)層連同物理層一起的全鏈路,分為雙節(jié)點(diǎn)AD/DA回環(huán)和多節(jié)點(diǎn)無線傳輸兩個(gè)場景進(jìn)行了詳細(xì)的測試。結(jié)果表明,實(shí)現(xiàn)后的網(wǎng)絡(luò)層配合物理層鏈路可以在100km范圍內(nèi)實(shí)現(xiàn)最小4.5ms的端到端延遲,提供最大約6.4Mbps的單向傳輸帶寬,可支持各種類型的以太網(wǎng)數(shù)據(jù)包,并實(shí)現(xiàn)4ns的同步精度。本文的研究內(nèi)容給出了一種基于FPGA的低延遲自組織網(wǎng)的解決方案,具有較強(qiáng)的可擴(kuò)展性,為自組織網(wǎng)的低延遲應(yīng)用提供了參考方案
[Abstract]:Unlike the traditional base-mobile terminal wireless network with central nodes, the wireless ad hoc network is a wireless network composed of several peer-to-peer devices. Due to the advantages of flexible network structure, independent networking and strong survivability, wireless ad hoc networks have become one of the important development directions of wireless communication technology. Wireless ad hoc networks usually use CSMA/CA or TDMA access mode, their end-to-end transmission delay is large, so it is not suitable for military communications. In order to solve the problem of long transmission delay of communication nodes in ad hoc networks, based on Ethernet interface and physical layer link, this paper designs and implements a competitive and time-division multiple access (TDMA) access and networking mode on FPGA. The high precision global time synchronization between nodes is realized. The main work of this paper is as follows: firstly, the existing access methods and the common time synchronization algorithms are discussed, and according to the time synchronization and data transmission scenarios of the airborne ad hoc network, As well as the constraints of physical layer link and hardware system, a clear network layer design index of low delay ad hoc network is proposed. Secondly, according to the design index, it is divided into three modules: broadcast channel, data channel and transceiver switch. The network layer scheme of low delay ad hoc network is designed, which is used to realize node entry and exit network and high precision time synchronization, respectively. User IP traffic data transmission and TDD channel access control are three main functions, and a flexible switching process between competing access mode and time division multiple access mode is given. Then, the FPGA implementation details of broadcast channel, data channel and transceiver switch are discussed in detail, including the overall structure block diagram of each module, the state transition of each sub-module, the process of framing and unframing. And the transceiver switching control of competition and time division multiple access (TDMA) mode, and a method of link management through the UDP configuration channel of Ethernet interface is presented. Finally, the whole link of network layer and physical layer is divided into two scenarios: two-node AD/DA loop and multi-node wireless transmission. The results show that the realized network layer with physical layer link can realize the end-to-end delay of the minimum 4.5ms in the range of 100km, provide the maximum one-way transmission bandwidth of about 6.4Mbps, support all kinds of Ethernet packets, and realize the synchronization accuracy of 4ns. In this paper, a solution of low delay ad hoc network based on FPGA is presented, which has strong extensibility and provides a reference scheme for low delay application of ad hoc network.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN791

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 崔鶴;劉云清;盛家進(jìn);;基于FPGA的UDP/IP協(xié)議棧的研究與實(shí)現(xiàn)[J];長春理工大學(xué)學(xué)報(bào)(自然科學(xué)版);2014年02期

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本文編號(hào)：1926161