本文選題：多級運算放大器 + 頻率補償�。� 參考：《北方工業(yè)大學》2015年碩士論文

【摘要】：運算放大器是集成電路的核心模塊,廣泛應用在數(shù)模轉(zhuǎn)換器,模數(shù)轉(zhuǎn)換器,電源管理等電路里。運放的性能直接影響了整體電路的性能,因此,運算放大器的設計成為當今集成電路領域的熱點問題。 隨著集成電路技術的不斷發(fā)展,電路集成度越來越高,MOS晶體管的尺寸越來越小,使電路設計逐漸進入深亞微米級。短溝道效應凸顯,使得單級放大電路的本征增益減小。傳統(tǒng)的兩級運算放大電路已經(jīng)不能滿足需求。需要采用多級級聯(lián)的方式獲得較高的電壓開環(huán)增益。但是,運算放大器的級聯(lián)引入了額外的極點和零點,影響了運算放大器的穩(wěn)定性。因此,需要采用頻率補償技術保證運算放大電路的閉環(huán)穩(wěn)定性。 本論文以傳統(tǒng)的兩級運算放大器為例,闡述了放大器的頻率補償原理,介紹了幾種多級運算放大器的頻率補償結構。基于SMIC0.18μm工藝設計了一種三級運算放大器,在提供較大直流增益的同時,增加了輸入輸出擺幅。采用了合適的頻率補償結構對其進行補償,仿真結果表明,本文所設計的三級運算放大器在3.3v電源電壓下,負載為5pf電容時,直流開環(huán)增益為155dB,單位增益帶寬達到了32MHz,相位裕度為56.09。,具有較理想的頻率響應和瞬態(tài)響應,并且所需的補償電容值較小,優(yōu)化了芯片的面積,較容易在CMOS工藝下實現(xiàn)。增益和相位裕度均滿足設計要求。
[Abstract]:Operational amplifier is the core module of integrated circuit. It is widely used in digital-to-analog converter, A / D converter, power management and so on. The performance of operational amplifier directly affects the performance of the whole circuit. Therefore, the design of operational amplifier has become a hot issue in the field of integrated circuit. With the development of integrated circuit technology, the size of MOS transistor becomes smaller and smaller, which makes the circuit design gradually enter deep sub-micron level. The short channel effect is prominent, which reduces the intrinsic gain of single stage amplifier. The traditional two-stage operation amplifier can not meet the demand. High voltage open loop gain is needed by multistage cascade. However, the cascade of operational amplifiers introduces additional poles and zeros, which affects the stability of operational amplifiers. Therefore, frequency compensation technique is needed to ensure the closed-loop stability of the operational amplifier. This paper takes the traditional two-stage operational amplifier as an example, expounds the principle of frequency compensation of amplifier, and introduces several kinds of multi-stage operational amplifier's frequency compensation structure. Based on SMIC0.18 渭 m process, a three-stage operational amplifier is designed, which not only provides a large DC gain, but also increases the input and output swing. The simulation results show that the three-stage operational amplifier designed in this paper is loaded with 5pf capacitor at 3.3v power supply voltage. The DC open-loop gain is 155dB, the unit gain bandwidth is 32MHz, the phase margin is 56.09.It has ideal frequency response and transient response, and the compensation capacitance is small. The area of the chip is optimized and it is easy to realize in CMOS process. Both gain and phase margin meet the design requirements.
【學位授予單位】：北方工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN722.77

【參考文獻】

相關期刊論文 前5條

1 何崢嶸;;運算放大器電路的噪聲分析和設計[J];微電子學;2006年02期

2 周瑋;吳貴能;李儒章;;一種高電源抑制比CMOS運算放大器[J];微電子學;2009年03期

3 朱治鼎;彭曉宏;呂本強;李曉慶;;高性能折疊式共源共柵運算放大器的設計[J];微電子學;2012年02期

4 黃曉宗;黃文剛;劉倫才;晏開華;何崢嶸;王成鶴;王國強;;運算放大器共模抑制比的仿真與測試[J];微電子學;2012年02期

5 李強,易俊,李肇基,張波;A Novel Frequency Compensation Technique for Three-Stage Amplifier[J];Journal of Electronic Science and Technology of China;2005年02期

，

本文編號：1923048