本文選題：高速 + 高密度��； 參考：《西南交通大學》2015年碩士論文

【摘要】：高速高密度電路板是現(xiàn)階段電子系統(tǒng)發(fā)展的必然趨勢,在強輻射源與高功率微波領域中,由高速和高密度環(huán)境引起的信號完整性和電源完整性問題不容忽視。本文針對某基于FPGA電機控制系統(tǒng)的高速高密度電路板,分析其板級信號完整性和電源完整性問題,以及連接器的信號完整性問題。本文對高速高密度PCB信號完整性和電源完整性進行研究。首先,明確高速、高密度、信號完整性和電源完整性的基本概念,調研國內外信號完整性和電源完整性的研究現(xiàn)狀,分析其產生原因和表現(xiàn)形式,如串擾、反射和同步開關噪聲等,并對這些表現(xiàn)形式進行深入研究,分析其產生的根本原因、影響因素和減小不良影響的方法。其次,對該PCB進行層疊結構的分析和設計,通過傳輸線類型的分析和特性阻抗的計算得到不同信號層傳輸線的線寬及厚度,預估計串擾影響,根據(jù)3W原則、3H原則和布線需求得到線距,完成布局和布線的設計。利用FPGA的可編程性建立高低速混合模型,根據(jù)電機控制信號線和SDRAM信號線時序要求的不同,選擇恰當?shù)腎BIS驅動器模型,建立時域電路模型進行時域仿真,得到傳輸線的傳輸特性,并選擇多跟相鄰傳輸線進行串擾分析。然后,對FPGA負載進行最優(yōu)化設計,通過仿真計算Z-f曲線和電源紋波,分析兩種不同負載方案的優(yōu)劣并確定負載方案。根據(jù)Z-f曲線設計去耦網(wǎng)絡,添加去耦電容,降低目標阻抗以減小電源紋波。在完成優(yōu)化負載和去耦網(wǎng)絡設計的基礎上,從理論分析和仿真驗證的角度,分析過孔結構對電源分配網(wǎng)絡性能的影響,得到過孔內徑、焊盤和反焊盤的最佳設計尺寸,指出除了傳統(tǒng)的優(yōu)化負載設計和添加去耦電容的方式之外,還可以通過修改過孔結構優(yōu)化電源紋波,實現(xiàn)電源紋波的最優(yōu)化設計。對電機控制板與電機之間某型號連接器進行仿真分析。運用仿真軟件對其3D建模,運用場路結合的分析方法,計算其S參數(shù),提取并導入時域仿真軟件,得到連接器的傳輸特性。取相鄰的多對引腳進行分析,仿真計算其串擾影響。對比傳統(tǒng)的阻抗匹配方式進行優(yōu)化,指出阻抗匹配法的局限性；采用從高速到低速轉換的方法,完成連接器傳輸特性的優(yōu)化,使連接器在PCB中得以良好的運用。根據(jù)前文仿真內容完成PCB的設計并加工,得到實物。用示波器對加工完成的PCB進行測試分析,得到單根傳輸線的傳輸特性,對比仿真結果,驗證PCB傳輸線具有良好的傳輸特性。測試電容引腳兩端電源紋波,驗證PCB的電源紋波滿足應用需求,具有較好的電源完整性。
[Abstract]:High speed and high density circuit board is the inevitable trend of electronic system development at present. In the field of strong emitter and high power microwave, the signal integrity and power integrity caused by high speed and high density environment can not be ignored.In this paper, the problems of board level signal integrity, power supply integrity and connector signal integrity are analyzed for a high speed and high density circuit board based on FPGA motor control system.In this paper, the signal integrity and power integrity of high speed and high density PCB are studied.First of all, make clear the basic concepts of high speed, high density, signal integrity and power integrity, investigate the research status of signal integrity and power integrity at home and abroad, analyze their causes and manifestations, such as crosstalk,The reflection and synchronous switching noise and so on are studied in depth to analyze the root causes of these manifestations, the influencing factors and the methods to reduce the adverse effects.Secondly, the stack structure of the PCB is analyzed and designed. Through the analysis of transmission line type and the calculation of characteristic impedance, the line width and thickness of different signal layer transmission lines are obtained, and the influence of crosstalk is pre-estimated.According to the 3W principle and the routing requirement, the distance between the lines is obtained, and the layout and routing design is completed.The high and low speed hybrid model is established by using the programmability of FPGA. According to the different timing requirements of the motor control signal line and the SDRAM signal line, the appropriate IBIS driver model is selected, and the time domain circuit model is established to carry out the time domain simulation.The transmission characteristics of transmission lines are obtained, and crosstalk analysis of multiple adjacent transmission lines is carried out.Then, the optimal design of FPGA load is carried out. The Z-f curve and the power ripple are simulated and calculated. The advantages and disadvantages of the two different load schemes are analyzed and the load schemes are determined.According to Z-f curve, decoupling network is designed, decoupling capacitance is added, and target impedance is reduced to reduce the ripple of power supply.On the basis of the optimization of load and decoupling network design, from the angle of theoretical analysis and simulation verification, this paper analyzes the influence of the perforated structure on the performance of the power distribution network, and obtains the optimum design size of the overhole inner diameter, the pad and the reverse pad.It is pointed out that in addition to the traditional ways of optimizing load design and adding decoupling capacitors, the optimal design of power ripple can also be realized by modifying the structure of perforated power supply.A certain type of connector between motor control board and motor is simulated and analyzed.The 3D model was modeled by simulation software, and the S parameters were calculated by the method of field circuit analysis. The time domain simulation software was extracted and imported, and the transmission characteristics of the connector were obtained.Several pairs of adjacent pins are analyzed and the crosstalk effect is simulated.Compared with the traditional impedance matching method, the limitation of the impedance matching method is pointed out, and the transmission characteristics of the connector are optimized by using the method of high speed to low speed conversion, so that the connector can be well used in PCB.According to the above simulation content, the design and processing of PCB are completed, and the object is obtained.The transmission characteristics of a single transmission line are obtained by testing and analyzing the finished PCB by oscilloscope. The simulation results show that the PCB transmission line has good transmission characteristics.The power ripple at both ends of the capacitor pin is tested to verify that the power ripple of PCB meets the requirement of application and has good power integrity.
【學位授予單位】：西南交通大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN41

【參考文獻】

相關期刊論文 前8條

1 閆靜純;李濤;蘇浩航;;高速高密度PCB電源完整性分析[J];電子器件;2012年03期

2 馬秀成;楊曉非;;基于FPGA的高速信號采集系統(tǒng)的信號完整性分析[J];測控技術;2011年07期

3 周路;賈寶富;;信號上升或下降時間對高速電路信號完整性影響的研究[J];現(xiàn)代電子技術;2011年06期

4 徐文波;保長先;王健;;IBIS模型的信號完整性研究與仿真應用[J];機電工程;2011年01期

5 張華,洪偉;不完整地參考面對高速互連耦合及串擾的影響分析[J];東南大學學報(自然科學版);2005年05期

6 黎淑蘭,唐碧華,劉元安,陳海濱;微帶線間的串擾抑制分析[J];溫州師范學院學報(自然科學版);2005年02期

7 宋占海,劉元安,黎淑蘭,閆樹兵,葛永清;對垂直交叉線中串擾的分析[J];電波科學學報;2003年04期

8 于學萍,呂英華,馮曉俊,黃永明;割裂大地對數(shù)字信號的影響[J];電波科學學報;2002年05期

相關博士學位論文 前2條

1 張木水;高速電路電源分配網(wǎng)絡設計與電源完整性分析[D];西安電子科技大學;2009年

2 張華;高速互連系統(tǒng)的信號完整性研究[D];東南大學;2005年

相關碩士學位論文 前10條

1 肖然;高速連接器的仿真分析及優(yōu)化[D];北京郵電大學;2013年

2 葉小蘭;高速率電連接器信號完整性分析[D];北京郵電大學;2013年

3 李鈺峰;高速PCB電源完整性研究[D];北京郵電大學;2012年

4 張建新;高速PCB的信號和電源完整性問題研究[D];西安電子科技大學;2012年

5 朱亞地;高速PCB信號反射及串擾仿真分析[D];西安電子科技大學;2012年

6 張鵬;高速PCB板信號完整性仿真分析及應用[D];西安電子科技大學;2011年

7 何晴;高頻連接器性能分析[D];北京郵電大學;2011年

8 丁立濤;高速電路設計與信號完整性分析[D];西安電子科技大學;2011年

9 閆鐵錚;高速PCB信號完整性分析及硬件系統(tǒng)設計中的應用[D];廈門大學;2009年

10 鄭常斌;PCB信號完整性分析與設計[D];北京郵電大學;2008年

，

本文編號：1773834