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  本文選題：延時系統(tǒng)　切入點：鎖相環(huán)　出處：《電子科技大學》2015年碩士論文　論文類型：學位論文

【摘要】：高精度大動態(tài)延時系統(tǒng)在電子系統(tǒng)中有廣泛的應用空間。延時電路的研究方法呈現(xiàn)多元化,主要分為光纖延時、模擬電路延時、數字電路延時。每一類延時方法都有各自的優(yōu)缺點,很難同時滿足高精度、大動態(tài)范圍、集成化等性能指標。隨著FPGA技術的發(fā)展,提供了在器件內部構建高精度大動態(tài)延時系統(tǒng)的條件。由于FPGA芯片的許多優(yōu)良特性,廣泛應用于雷達系統(tǒng),延時系統(tǒng)與其他信號處理模塊集成于芯片內部,將會有非常重要的工程意義。本文從實際工程應用出發(fā),設計了一個對信號進行高精度大動態(tài)延時的系統(tǒng)。主要完成了以下工作。1.對延時電路的設計方案進行了歸納總結,得出高精度大動態(tài)延時電路的設計思路,分為粗細延時的策略。將FPGA相關的延時方案進行了深入的分析,總結了粗細延時在FPGA內部實現(xiàn)的各種設計方法。通過對比各種方案,確立了延時系統(tǒng)的設計方案。對延時系統(tǒng)方案中影響精度的關鍵因素進行了探討。2.延時系統(tǒng)設計方案中,核心的技術是對鎖相環(huán)進行高精度相位調整操作。詳細分析了鎖相環(huán)的原理與結構,并對器件內部嵌入的PLL結構進行了說明。對掃描鏈中參數之間的關系進行了梳理,重點介紹了鎖相環(huán)的重配置和動態(tài)相位調整功能。3.結合工程指標,完成了高精度大動態(tài)延時系統(tǒng)的整體設計與實現(xiàn),包括計數器延時模塊、具有動態(tài)相位調整功能的鎖相環(huán)模塊,同頻異相采樣模塊,線性調頻信號產生模塊,串口通信模塊。對每一模塊的設計原理和方法都做了說明。解決了異步時鐘采樣產生亞穩(wěn)態(tài)的問題。4.基于FPGA開發(fā)板,將整個延時系統(tǒng)的每一個模塊都做了細致的分析。利用仿真軟件對延時系統(tǒng)的高精度實現(xiàn)做了精確的分析。通過改變延時量,進行多次測量,分析出延時系統(tǒng)的誤差量,并總結出誤差的來源。驗證了設計的合理性與正確性。延時系統(tǒng)達到了性能指標。
[Abstract]:High precision and large dynamic delay system has wide application space in electronic system. The research methods of delay circuit are diversified, mainly divided into optical fiber delay, analog circuit delay, Digital circuit delay. Each type of delay methods have their own advantages and disadvantages, it is difficult to meet the high accuracy, large dynamic range, integration and other performance indicators. With the development of FPGA technology, The condition of constructing high precision and large dynamic delay system inside the device is provided. Because of many excellent characteristics of FPGA chip, it is widely used in radar system, and the delay system is integrated with other signal processing modules inside the chip. This paper designs a system of high precision and large dynamic delay for signal. 1. The design scheme of delay circuit is summarized. The design idea of high precision and large dynamic delay circuit is obtained, which is divided into thick and fine delay strategy. The delay schemes related to FPGA are analyzed deeply, and various design methods of realizing thick and fine delay in FPGA are summarized. The design scheme of the delay system is established. The key factors influencing the precision of the delay system scheme are discussed. 2. In the design scheme of the delay system, The key technology is to adjust the phase of PLL with high precision. The principle and structure of PLL are analyzed in detail, and the embedded PLL structure is explained. The reconfiguration of PLL and the function of dynamic phase adjustment. 3. Combined with engineering indexes, the overall design and implementation of high precision and large dynamic delay system are completed, including counter delay module. Phase-locked loop module with dynamic phase adjustment function, same frequency and different phase sampling module, linear frequency modulation signal generating module, Serial communication module. The design principle and method of each module are explained. The problem of asynchronous clock sampling to produce metastable state is solved. 4. Based on FPGA development board, Each module of the whole delay system is analyzed in detail. The high precision realization of the delay system is analyzed accurately by using the simulation software. The error of the delay system is analyzed by changing the delay quantity and measuring it many times. The source of the error is summarized. The rationality and correctness of the design are verified. The delay system achieves the performance index.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN791

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本文編號：1629245