本文選題：SPI　切入點(diǎn)：UVM　出處：《西安電子科技大學(xué)》2015年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：隨著SOC(System on Chip)設(shè)計(jì)規(guī)模的快速發(fā)展和IP(Intellectual Property)的大量采用,驗(yàn)證已經(jīng)成為了制約芯片設(shè)計(jì)的瓶頸。驗(yàn)證貫穿了整個(gè)芯片設(shè)計(jì)流程,高效的驗(yàn)證既可以保證設(shè)計(jì)功能的正確性,又能提高設(shè)計(jì)的生產(chǎn)率,為加速芯片上市時(shí)間提供強(qiáng)有力的保障。驗(yàn)證可以分為功能驗(yàn)證和時(shí)序驗(yàn)證兩大部分。本文主要研究的是SOC驗(yàn)證的核心——數(shù)字功能驗(yàn)證。首先調(diào)研當(dāng)前SoC的背景,研究的目的與意義以及國(guó)內(nèi)外研究現(xiàn)狀。證明驗(yàn)證的重要性。分析目前驗(yàn)證面臨的挑戰(zhàn),總結(jié)當(dāng)前主流的功能驗(yàn)證技術(shù),提出應(yīng)對(duì)這些挑戰(zhàn)所采用的一些驗(yàn)證技術(shù)和方法,包括約束隨機(jī)驗(yàn)證、覆蓋率驅(qū)動(dòng)驗(yàn)證和斷言等驗(yàn)證方法。SystemVerilog驗(yàn)證語(yǔ)言集成了面向?qū)ο缶幊桃约笆芗s束的隨機(jī)激勵(lì),為功能驗(yàn)證提供了強(qiáng)大的支持。UVM驗(yàn)證方法學(xué)是以SystemVerilog為基礎(chǔ)所建立的一個(gè)庫(kù),它提供了一系列的接口,使得驗(yàn)證平臺(tái)的搭建變得簡(jiǎn)單,從而能夠更方便的完成驗(yàn)證。SPI是一種常用的標(biāo)準(zhǔn)串行接口,Si4432是一款高性能射頻收發(fā)器。本文以Si4432芯片中的SPI控制接口為基礎(chǔ)實(shí)現(xiàn)芯片的功能驗(yàn)證。通過(guò)分析SPI協(xié)議,深入研究SPI的原理和基本結(jié)構(gòu),以及SPI工作模式、SPI傳輸模式。采用Verilog HDL語(yǔ)言完成了對(duì)SPI接口的設(shè)計(jì)。本文的重點(diǎn)是對(duì)設(shè)計(jì)的SPI進(jìn)行功能驗(yàn)證。先通過(guò)SPI的設(shè)計(jì)總結(jié)出了驗(yàn)證平臺(tái)的主要架構(gòu),然后結(jié)合UVM驗(yàn)證方法學(xué)設(shè)計(jì)并使用硬件驗(yàn)證語(yǔ)言編寫(xiě)了一個(gè)驗(yàn)證平臺(tái)。最后對(duì)驗(yàn)證平臺(tái)進(jìn)行優(yōu)化。采用虛接口完成多種激勵(lì)的同步,使驗(yàn)證平臺(tái)可以同時(shí)進(jìn)行寄存器的配置和正常包的發(fā)送。其次改用FIFO的形式連接組件,主要使記分板能共主動(dòng)接受數(shù)據(jù)。增加注入非正常激勵(lì)的功能,實(shí)現(xiàn)整個(gè)驗(yàn)證平臺(tái)的完備性。通過(guò)回調(diào)的方式,完成對(duì)驅(qū)動(dòng)器和監(jiān)視器的改進(jìn),使驗(yàn)證平臺(tái)能夠用于多個(gè)項(xiàng)目設(shè)計(jì)中,從而提高了驗(yàn)證平臺(tái)可重用性。本章最后對(duì)驗(yàn)證平臺(tái)進(jìn)行覆蓋率的測(cè)試。通過(guò)觀測(cè)功能覆蓋率來(lái)調(diào)整驗(yàn)證激勵(lì)的生成方式,讓激勵(lì)盡可能完備,使代碼覆蓋率和功能覆蓋率都達(dá)到100%,實(shí)現(xiàn)驗(yàn)證平臺(tái)的正確性并且完成對(duì)SPI設(shè)計(jì)的驗(yàn)證。
[Abstract]:With the rapid development of SOC(System on chip design scale and the large adoption of IP(Intellectual property, verification has become the bottleneck of chip design. Can also improve the productivity of the design, The verification can be divided into two parts: functional verification and timing verification. This paper mainly studies the core of SOC verification-digital functional verification. Firstly, the background of current SoC is investigated. The purpose and significance of the research, the status quo of research at home and abroad, the importance of proof verification, the analysis of the challenges faced by the current verification, the summary of the current mainstream functional verification technologies, and some verification techniques and methods used to deal with these challenges are put forward. The verification methods, such as constrained random verification, coverage driven verification and assertion, integrate object-oriented programming and constrained random excitation. It provides powerful support for functional verification. UVM verification methodology is a library based on SystemVerilog. It provides a series of interfaces, which make it easy to build verification platform. Therefore, it is more convenient to complete verification. SPI is a common standard serial interface, Si4432 is a high performance RF transceiver. This paper realizes the functional verification of Si4432 chip based on the SPI control interface. By analyzing the SPI protocol, this paper analyzes the SPI protocol. Deeply study the principle and basic structure of SPI, The Verilog HDL language is used to complete the design of the SPI interface. The emphasis of this paper is to verify the function of the designed SPI. Firstly, the main framework of the verification platform is summarized through the design of the SPI. Then a verification platform is designed with UVM verification methodology and hardware verification language. Finally, the verification platform is optimized, and the virtual interface is used to complete the synchronization of various excitations. The verification platform can configure registers and send normal packets at the same time. Secondly, the components can be connected in the form of FIFO, so that the scorecard can accept the data actively and increase the function of injecting abnormal excitation. The implementation of the integrity of the entire verification platform. Through the callback way, complete the improvement of the driver and monitor, so that the verification platform can be used in multiple project design, In the end of this chapter, the coverage of the verification platform is tested. The generation of validation incentive is adjusted by the coverage of observation function to make the incentive as complete as possible. Make the code coverage and function coverage reach 100, verify the correctness of the platform and complete the verification of the SPI design.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN402

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本文編號(hào)：1588892