本文選題：功能驗證　切入點：SVA　出處：《西安電子科技大學》2015年碩士論文　論文類型：學位論文

【摘要】：隨著集成電路一直在向高性能、高集成度、低功耗的SoC方向發(fā)展,功能驗證在設計開發(fā)過程中變得越來越復雜和越來越重要。傳統(tǒng)的驗證技術和方法在開發(fā)周期,驗證效率以及驗證平臺的可觀性、可控性和可復用性等方面的表現(xiàn)已經不能夠滿足當前的需求。伴隨著電子設計自動化技術的快速發(fā)展,各種各樣的新型的驗證技術和方法就如何提高驗證效率,縮短開發(fā)周期以及開發(fā)可移植的驗證組件和環(huán)境等方面做了很多的探索,他們已經在諸多方面彌補了傳統(tǒng)驗證技術和方法的不足。本文基于斷言驗證方法,主要研究了System Verilog Assertion的功能驗證技術在實際項目中的應用。根據(jù)SVA的語言與驗證技術特點,分析闡述了其在驗證環(huán)境開發(fā)和使用過程中的優(yōu)勢。針對中斷延遲控制器,提出了一個單靠形式化方法的功能驗證設計方案,根據(jù)其功能規(guī)范的要求,使用SVA編寫了用于斷言和假設的屬性,通過Jasper形式驗證技術,實現(xiàn)了驗證平臺的搭建以及完成了該模塊的功能驗證工作。該方法在保證驗證質量的同時有效的縮短了開發(fā)周期,提高了驗證效率。另外,基于當前流行的OVM驗證方法學對通用輸入輸出控制模塊提出了一種斷言覆蓋率驅動的驗證設計方案,在OVM類庫的基礎上實現(xiàn)了用于待測設計的OVC組件,通過斷言模塊的功能檢測和覆蓋率分析搭建了一個完整的驗證平臺,實現(xiàn)了一個高層次化,高覆蓋率,可復用性強的驗證環(huán)境。本文研究開發(fā)的驗證環(huán)境和平臺成功的完成了待測設計的功能驗證,并已經應用到實際的項目中。中斷延遲控制器的形式化驗證方法已經推廣到其他相似功能模塊的驗證工作,通用輸入輸出控制模塊的驗證組件和斷言模塊很好的復用到其他的項目。研究結果和實踐表明,基于SVA的驗證技術和方法實現(xiàn)的形式驗證環(huán)境的功能覆蓋率達到100%,并且有效地節(jié)省了開發(fā)時間,縮短了的驗證周期;實現(xiàn)的OVM驗證平臺具有很高的可復用性,并且其功能覆蓋率達到100%,代碼覆蓋率達到97.9%。
[Abstract]:With the development of integrated circuits in the direction of high performance, high integration and low power consumption, functional verification has become more and more complex and important in the process of design and development. The performance of verification efficiency and the observability, controllability and reusability of the verification platform can no longer meet the current needs. With the rapid development of electronic design automation technology, Various new verification technologies and methods have done a lot of research on how to improve the efficiency of verification, shorten the development cycle and develop portable verification components and environments. They have made up for the shortcomings of traditional verification techniques and methods in many aspects. Based on the assertion verification method, this paper mainly studies the application of System Verilog Assertion function verification technology in actual projects. According to the characteristics of SVA language and verification technology, This paper analyzes and expounds its advantages in the process of developing and using the verification environment. For interrupt delay controller, a design scheme of function verification based on formal method is proposed, according to the requirements of its function specification. The attributes used for assertion and hypothesis are written with SVA, and the verification platform is built and the function verification work of the module is completed by means of Jasper formal verification technology. This method can effectively shorten the development period while guaranteeing the verification quality. In addition, based on the popular OVM verification methodology, an assertion coverage driven verification design scheme is proposed for the general input and output control module. Based on the OVM class library, a OVC component is implemented for the design to be tested. Through the function detection and coverage analysis of the assertion module, a complete verification platform is built, which realizes a high level and high coverage. The verification environment and platform developed in this paper have successfully completed the functional verification of the design to be tested. The formal verification method of interrupt delay controller has been extended to other similar functional modules. The verification components and assertion modules of the Universal I / O control module are well reused to other projects. The function coverage of formal verification environment based on SVA is 100, and the development time is saved and the verification cycle is shortened. The OVM verification platform has high reusability. And its function coverage rate reaches 100%, the code coverage rate reaches 97.9%.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN407

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本文編號：1588722