本文選題：數(shù)字預(yù)失真　切入點(diǎn)：高效功率放大器　出處：《電子科技大學(xué)》2015年碩士論文　論文類(lèi)型：學(xué)位論文

【摘要】：高效功率放大器作為發(fā)射鏈路的末級(jí),其功能是將發(fā)射信號(hào)進(jìn)行功率放大。但是隨著通信技術(shù)的發(fā)展,新的通信模式對(duì)高效功率放大器提出了新的挑戰(zhàn)。首先業(yè)務(wù)需求量的增加導(dǎo)致調(diào)制方式由恒包絡(luò)向非恒包絡(luò)轉(zhuǎn)變,提高了信號(hào)峰均比,影響了系統(tǒng)的通信質(zhì)量;其次傳輸帶寬的增加對(duì)線性化技術(shù)提出了新的要求。為了充分利用頻譜資源,采用了新的調(diào)制解調(diào)方式(QPSK,64QAM,OFDM等),這就要求改善功放的非線性失真;最后對(duì)功率放大器的數(shù)學(xué)建模增加了工程實(shí)現(xiàn)的復(fù)雜度。采用Volterra級(jí)數(shù)建模,隨著其階數(shù)的提高,工程實(shí)現(xiàn)的復(fù)雜度呈現(xiàn)指數(shù)增長(zhǎng),計(jì)算成本增大。針對(duì)以上面臨的問(wèn)題,本文給出了一種實(shí)現(xiàn)簡(jiǎn)單、工程成本低、線性補(bǔ)償能力強(qiáng)并且效率高的寬帶功放數(shù)字預(yù)失真實(shí)現(xiàn),具體包括以下方面:(1)通過(guò)分析寬帶功放數(shù)字預(yù)失真的關(guān)鍵技術(shù),提出了寬帶功放數(shù)字預(yù)失真系統(tǒng)的需求,然后從模型辨識(shí)算法(LMS算法、LS算法、RLS算法)、功放模型(Volterra級(jí)數(shù)、MP模型、SRPV模型)和查找表結(jié)構(gòu)等方面進(jìn)行方案的設(shè)計(jì)分析。(2)寬帶功放數(shù)字預(yù)失真的FPGA(Field Programable Gate Aray)設(shè)計(jì)實(shí)現(xiàn)。按照FPGA開(kāi)發(fā)流程,將工程劃分為五個(gè)模塊,分別是信號(hào)產(chǎn)生、輸出功率調(diào)整、數(shù)字預(yù)失真計(jì)算、多項(xiàng)式參數(shù)產(chǎn)生和高速數(shù)據(jù)采集接口并對(duì)其進(jìn)行設(shè)計(jì),并且對(duì)FPGA的資源使用進(jìn)行分析。(3)進(jìn)行寬帶功放數(shù)字預(yù)失真的性能測(cè)試與分析。搭建寬帶功放數(shù)字預(yù)失真的系統(tǒng)驗(yàn)證平臺(tái),對(duì)數(shù)字預(yù)失真的性能進(jìn)行測(cè)試。首先測(cè)試ADC接口和DAC接口,然后分別對(duì)帶寬為100MHz和20MHz的信源進(jìn)行系統(tǒng)測(cè)試并達(dá)到技術(shù)指標(biāo)要求。本文的研究驗(yàn)證了可以用FPGA芯片完成數(shù)字預(yù)失真設(shè)計(jì),并能達(dá)到改善功放非線性失真的效果,對(duì)工程應(yīng)用的可行性與有效性提供了依據(jù)。在數(shù)字部分做預(yù)失真也降低了工程復(fù)雜度和運(yùn)行成本。
[Abstract]:As the last stage of transmission link, the function of high efficiency power amplifier is to amplify the transmitted signal. But with the development of communication technology, The new communication mode poses a new challenge to the high efficiency power amplifier. Firstly, the increase of service demand leads to the change of modulation mode from constant envelope to non-constant envelope, which improves the PAPR and affects the communication quality of the system. Secondly, the increase of transmission bandwidth puts forward new requirements for linearization technology. In order to make full use of the spectrum resources, a new modulation and demodulation method is adopted, such as QPSKZ64QAM OFDM, which requires the improvement of nonlinear distortion of power amp; amp; amp; amp; amp; amp; amp; amp; amp; amp; amp; amp; amp; amp; Finally, the mathematical modeling of power amplifier increases the complexity of engineering implementation. With the increase of order of Volterra series, the complexity of engineering implementation increases exponentially and the computational cost increases. This paper presents a digital predistortion realization of wideband power amplifier with simple implementation, low engineering cost, strong linear compensation ability and high efficiency, including the following aspects: 1) by analyzing the key technology of broadband power amplifier digital predistortion, The requirement of wideband power amplifier digital predistortion system is put forward. Then, the design and implementation of FPGA(Field Programable Gate Aray for digital predistortion of wideband power amplifier are carried out from the following aspects: model identification algorithm / LMS algorithm / LS algorithm / RLS algorithm, power amplifier model / Volterra series / MP model / SRPV model) and lookup table structure etc. Follow the FPGA development process, The project is divided into five modules: signal generation, output power adjustment, digital predistortion calculation, polynomial parameter generation and high-speed data acquisition interface. And the resource usage of FPGA is analyzed. (3) the performance test and analysis of digital predistortion of broadband power amplifier are carried out, and the system verification platform of digital predistortion of broadband power amplifier is built. Test the performance of digital predistortion. First test the ADC interface and DAC interface. Then the signal sources with bandwidth of 100MHz and 20MHz are tested and the technical requirements are met. The research of this paper verifies that the digital predistortion design can be completed by using FPGA chip, and the nonlinear distortion of power amplifier can be improved. It provides the basis for the feasibility and validity of engineering application, and reduces the complexity and operation cost of the project by pre-distortion in the digital part.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN722.75

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 陳軍;數(shù)字預(yù)失真多項(xiàng)式的FPGA實(shí)現(xiàn)[D];華南理工大學(xué);2010年

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本文編號(hào)：1586704