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  本文關鍵詞： 演化硬件 笛卡爾遺傳規(guī)劃 進化算法 在線進化設計　出處：《河北師范大學》2017年碩士論文　論文類型：學位論文

【摘要】：隨著社會的發(fā)展與科技的進步,電子系統不斷趨于微型化、智能化,規(guī)模和復雜程度不斷增加,與此同時,電子系統的可靠性也已經成為其發(fā)展過程中的巨大挑戰(zhàn),演化硬件的出現為處理這一問題提供了解決方案。演化硬件是進化算法與可編程邏輯器件的有機結合體,它能夠像生物一樣根據環(huán)境的變化自主、動態(tài)地調整自身結構,提高在惡劣環(huán)境下硬件的穩(wěn)定性及可靠性,延長硬件的使用壽命�，F場可編程門陣列(Field Programmable Gate Array,FPGA)作為可編程器件的最新發(fā)展成果,具有靈活方便、無限可重構的特性,被廣泛用作為演化硬件的實現載體。將進化算法與可進化硬件電路在同一片FPGA上構成片上演化系統,是將演化硬件付諸工程應用,構成自適應和容錯硬件系統的重要途徑。本文研究了演化硬件的基本原理與關鍵技術,并在現場可編程門陣列FPGA芯上設計了NiosII嵌入式軟核處理器CPU、虛擬可重構電路解碼器VRC、在線評估通信模塊,并由這三個分模塊組成了片上電路在線進化設計平臺,利用該平臺進行了片上電路進化試驗研究。主要研究內容如下:1.采用笛卡爾遺傳規(guī)劃CGP作為進化算法對電路進化設計進行研究,研究了染色體變異率與進化收斂速度之間的關系,得出了在給定的基因長度情況下的最優(yōu)變異位數。2.研究了基于FPGA的片上電路進化設計平臺。在FPGA芯片上利用設計的NiosII嵌入式軟核處理器CPU,虛擬可重構電路解碼器VRC、在線評估通信模塊,完成了片上電路進化平臺的構建。NiosII嵌入式軟核處理器CPU執(zhí)行進化算法,通過進化計算得出新一代種群;VRC虛擬可重構電路解碼器對種群中的每個染色體進行解碼,并在FPGA芯片上自動構建與該染色體相對應的電路;在線評估通信模塊實現通過對構建的電路進行數據采集,并實時的將所采集的數據反饋到NiosII軟核處理器,實現了電路的片上在線進化設計。并通過構建的平臺對全加器和乘法器進行了片上電路在線進化設計試驗研究。3.對同步時序電路的片上進化設計進行了研究。在設計的電路進化設計平臺的基礎上,對VRC虛擬可重構電路解碼器進行改進。將D觸發(fā)器與組合電路的VRC虛擬可重構電路解碼器相結合構建了可進化時序電路的VRC虛擬可重構電路解碼器;并通過改進的平臺實現了時序電路的片上進化設計;利用該平臺對模六計數器與1010序列檢測器進行了進化設計研究。
[Abstract]:With the development of society and the progress of science and technology, electronic system is becoming more and more miniaturized, intelligent, scale and complexity. At the same time, the reliability of electronic system has become a great challenge in its development. The emergence of evolutionary hardware provides a solution to this problem. Evolutionary hardware is an organic combination of evolutionary algorithms and programmable logic devices. In order to improve the stability and reliability of hardware in harsh environment and prolong the service life of hardware, Field Programmable Gate FPGA (Field Programmable Gate Array), as the latest development achievement of programmable devices, has the characteristics of flexibility, convenience and infinite reconfiguration. It is widely used as the implementation carrier of evolutional hardware. The evolutionary hardware is put into engineering application by using evolutionary algorithm and evolutive hardware circuit on the same piece of FPGA to form the system of evolution on a chip. This paper studies the basic principles and key technologies of evolutionary hardware. NiosII embedded soft core processor, virtual reconfigurable circuit decoder, on-line evaluation communication module are designed on the FPGA core of field programmable gate array, and the on-chip circuit on-line evolution design platform is made up of these three modules. The main contents are as follows: 1. Descartes genetic programming (CGP) is used as the evolutionary algorithm to study the circuit evolution design. The relationship between the rate of chromosome variation and the rate of convergence of evolution is studied. The optimal number of variances in given gene length is obtained. 2. The design platform of on-chip circuit evolution based on FPGA is studied. The virtual reconfigurable circuit decoder based on NiosII embedded soft core processor is designed on FPGA chip. VRC, online evaluation communication module, The construction of on-chip circuit evolution platform. Nios II embedded soft core processor CPU performs evolutionary algorithm. By evolutionary calculation, a new generation of population VRC virtual reconfigurable circuit decoder is obtained to decode each chromosome in the population. The circuit corresponding to the chromosome is automatically constructed on the FPGA chip, and the on-line evaluation communication module realizes the data acquisition through the constructed circuit, and the collected data is fed back to the NiosII soft core processor in real time. The on-chip evolution design of the circuit is realized, and the on-chip circuit on-line evolutionary design of the full adder and multiplier is studied by using the constructed platform. 3. The on-chip evolutionary design of the synchronous sequential circuit is studied in this paper. Based on the design of the circuit evolution design platform, The VRC virtual reconfigurable circuit decoder is improved. The VRC virtual reconfigurable circuit decoder of evolutionary sequential circuit is constructed by combining D flip-flop with VRC virtual reconfigurable circuit decoder of combinational circuit. The on-chip evolutionary design of sequential circuits is realized by using the improved platform, and the evolutionary design of modular sixth counter and 1010 sequence detector is studied by using this platform.
【學位授予單位】：河北師范大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN47

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