本文關(guān)鍵詞： FPGA SKEW 環(huán)形振蕩器 測(cè)試　出處：《微電子學(xué)與計(jì)算機(jī)》2017年06期 　論文類型：期刊論文

【摘要】：隨著FPGA規(guī)模的擴(kuò)大和工作頻率的提高,時(shí)鐘Skew成為FPGA越來(lái)越重要的性能指標(biāo),而如何精確測(cè)試芯片中的時(shí)鐘Skew也就顯得尤為重要.對(duì)此以JFPGA-YX2芯片為例,介紹一種可以精確測(cè)量FPGA時(shí)鐘Skew的測(cè)試方法.將芯片內(nèi)部的時(shí)鐘資源通過(guò)配置邏輯配置成一系列的環(huán)形振蕩器,每個(gè)振蕩器的振蕩頻率由該振蕩器所包含路徑的延時(shí)決定.對(duì)這些振蕩器的測(cè)量頻率值進(jìn)行運(yùn)算處理即可獲得精確的時(shí)鐘Skew.
[Abstract]:With the expansion of FPGA and the increase of the frequency of clock, Skew becomes more and more important performance index of FPGA, and how to accurately test the clock chip Skew is particularly important. This is based on JFPGA-YX2 chip as an example, introduces a precise measurement of FPGA clock Skew test method. The chip internal clock resources through the configuration logic configuration into a series of ring oscillator, oscillation frequency of each oscillator by the oscillator contains path delay decision. Measuring frequency of these oscillators are processed to obtain the exact value of the clock Skew.

【作者單位】： 無(wú)錫中微億芯有限公司;中國(guó)電子科技集團(tuán)公司第五十八研究所;
【基金】：國(guó)家科技重大專項(xiàng)資助項(xiàng)目(2015ZX01018101-005)
【分類號(hào)】：TN791
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本文編號(hào)：1531997