本文關(guān)鍵詞： 電力線載波 自動(dòng)抄表 發(fā)送端 數(shù)模轉(zhuǎn)換器 線驅(qū)動(dòng)　出處：《湘潭大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：近年來(lái),借助物聯(lián)網(wǎng)技術(shù)高速發(fā)展的東風(fēng),電力事業(yè)在蓬勃向前。然而,包括電卡充值系統(tǒng)、掌上抄表計(jì)算機(jī)、無(wú)線遠(yuǎn)程抄表在內(nèi)的現(xiàn)存的用電統(tǒng)計(jì)與管理手段都并非實(shí)惠與全面。作為一種可供選擇的手段,電力線載波通信進(jìn)入了人們的視野。以低壓供電線充當(dāng)通信介質(zhì),具有機(jī)械強(qiáng)度高、可靠性好以及分布廣泛等特點(diǎn),具有優(yōu)秀的實(shí)用價(jià)值,并將給電力公司帶來(lái)可觀的經(jīng)濟(jì)效益�，F(xiàn)階段基于低壓電力線載波通訊的自動(dòng)抄表系統(tǒng)中所使用的多數(shù)為國(guó)外芯片,在增加了居民用戶和電力企業(yè)的經(jīng)濟(jì)壓力的同時(shí),也給國(guó)家電力系統(tǒng)的安全帶來(lái)風(fēng)險(xiǎn)�？梢哉f(shuō)底層電路芯片已經(jīng)成為我國(guó)低壓電力線載波通訊自動(dòng)抄表系統(tǒng)的制擎。本文根據(jù)課題需要,分析了電力線載波智能抄表技術(shù)的基本原理,研究了自動(dòng)抄表芯片中的基本模塊,詳細(xì)設(shè)計(jì)了基于電力線載波自動(dòng)抄表芯片模擬發(fā)送端電路,包括數(shù)字模擬轉(zhuǎn)換器電路(DAC),濾波器(Filter),線驅(qū)動(dòng)器(Line Driver)三個(gè)模塊。所做的設(shè)計(jì)工作基于SMIC 0.18μm 1P6M CMOS工藝。采用10 bit分段式電流舵DAC將數(shù)字信號(hào)轉(zhuǎn)換成模擬信號(hào),動(dòng)態(tài)參數(shù)后仿真結(jié)果為SNDR=61.3 dB,SNR=61.55 dB,THD=-74 dB,SFDR=76.35 dB,ENOB=9.89 bit,靜態(tài)參數(shù)差分輸出DNL=0.18719 LSB,INL=0.17187 LSB。采用3階切比雪夫2型低通濾波器實(shí)現(xiàn)對(duì)DAC轉(zhuǎn)換的模擬信號(hào)的濾波和平滑,其低頻增益為-765 mdB,截止頻率為521 KHz@3 d B,阻帶衰減起始頻率為803 KHz,阻帶衰減為-20.9 dB。并通過(guò)由預(yù)放大級(jí)和驅(qū)動(dòng)級(jí)構(gòu)成的線驅(qū)動(dòng)電路對(duì)信號(hào)進(jìn)行擺幅可調(diào)和功率放大輸出,在低至幾個(gè)歐姆的負(fù)載條件下,其單端輸出擺幅為2 V,最大輸出電流600 mA時(shí),總諧波失真小于-60 d B。以上指標(biāo)顯示,所設(shè)計(jì)的發(fā)送端通路不僅實(shí)現(xiàn)了數(shù)模轉(zhuǎn)換、低通濾波和功率放大的功能,而且保證了信號(hào)通路具有良好的線性度特性。最后,對(duì)發(fā)送端電路進(jìn)行了版圖實(shí)現(xiàn),為了保證良好的性能,特別考慮了電流舵DAC以及線驅(qū)動(dòng)電路功率管的版圖設(shè)計(jì)。
[Abstract]:In recent years, with the rapid development of the Internet of things technology, the power industry is booming. However, it includes card charging system, handheld meter reading computer. The existing power statistics and management methods, including wireless remote meter reading, are not affordable and comprehensive. Power line carrier communication has entered people's field of vision. With the characteristics of high mechanical strength, good reliability and wide distribution, the low voltage power supply line is used as the communication medium. It has excellent practical value. And it will bring considerable economic benefits to the power company. At this stage, most of the automatic meter reading system based on low-voltage power line carrier communication is used by foreign chips. At the same time, it increases the economic pressure of residents and electric power enterprises. It can be said that the underlying circuit chip has become the system of low-voltage power line carrier communication automatic meter reading system. The basic principle of intelligent meter reading technology based on power line carrier is analyzed, the basic module of automatic meter reading chip is studied, and the analog transmitter circuit based on power line carrier automatic meter reading chip is designed in detail. Include digital analog converter circuit DACU, filter filter. Line driver Line driver). Three modules. The design is based on SMIC 0.18 渭 m 1P6M CMOS process. 10 bit segmented current rudder DAC is used to convert digital signal into analog signal. The simulation results after dynamic parameters are as follows: 61.55 dBU THD -74 dB SFDR is 76.35 dB. ENOB=9.89 bit. static parameter differential output DNL=0.18719 LSB. INL=0.17187 LSB.Three order Chebyshev 2 low-pass filter is used to filter and smooth the analog signal converted by DAC. Its low frequency gain is -765 mdB. The cut-off frequency is 521 KHz@3 dB and the initial frequency of stopband attenuation is 803 KHz. The stopband attenuates to -20.9 dB, and the signal is amplified by a linear drive circuit composed of a preamplifier stage and a drive stage, which can amplify the signal in amplitude and harmonic power, under load conditions as low as several ohms. When the output swing is 2 V and the maximum output current is 600 Ma, the total harmonic distortion is less than -60 dB. Low pass filter and power amplification function, and ensure that the signal path has good linearity. Finally, the layout of the transmitter circuit is implemented to ensure good performance. Especially, the layout design of the current rudder DAC and the power transistor of the linear drive circuit is considered.
【學(xué)位授予單位】：湘潭大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TM933.4;TN402

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本文編號(hào)：1490343