本文關(guān)鍵詞：HEVC解碼器在異構(gòu)計(jì)算平臺(tái)上的設(shè)計(jì)及節(jié)能算法研究　出處：《山東大學(xué)》2017年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： HEVC解碼器 CPU GPU DVFS 視頻緩沖區(qū)

【摘要】：隨著網(wǎng)絡(luò)視頻業(yè)務(wù)的飛速發(fā)展,視頻流量在互聯(lián)網(wǎng)中逐漸占據(jù)主導(dǎo)地位。一項(xiàng)名為思科可視化網(wǎng)絡(luò)指數(shù)的計(jì)劃中指出:到2020年,每秒將會(huì)有100萬(wàn)分鐘的視頻內(nèi)容流經(jīng)網(wǎng)絡(luò),全球IP視頻流量占所有IP流量(企業(yè)和消費(fèi)者)的比例增加到82%。與此同時(shí),高清和超高清視頻越來(lái)越受到人們的關(guān)注與推崇。下一代視頻編碼標(biāo)準(zhǔn)High Efficiency Video Coding(HEVC/H.265)相比于現(xiàn)在廣泛采用的AVC/H.264視頻編碼標(biāo)準(zhǔn),在達(dá)到相同視頻質(zhì)量要求的前提下,可以實(shí)現(xiàn)更高的壓縮比。這主要是由于在HEVC視頻編碼標(biāo)準(zhǔn)中新增了許多有助于提高編碼性能的壓縮技術(shù),如可變大小的編碼樹(shù)單元、獨(dú)立并行編碼單元Tile以及多層次環(huán)路濾波等技術(shù)。然而,這些新技術(shù)在提高HEVC標(biāo)準(zhǔn)編碼效率的同時(shí),也增加了視頻編解碼實(shí)現(xiàn)的復(fù)雜度。跟據(jù)論文統(tǒng)計(jì),在相同編碼質(zhì)量的前提下,HEVC標(biāo)準(zhǔn)編碼復(fù)雜度提高了 5.2倍,相應(yīng)的解碼器復(fù)雜度提高了 2.1倍。目前,一些頂端的消費(fèi)電子廠商通過(guò)ASIC硬件電路實(shí)現(xiàn)了對(duì)HEVC編解碼的支持,如Intel、Apple、NVIDIA、AMD、華為等。然而,由于HEVC解碼器的計(jì)算復(fù)雜度較高,對(duì)于電池供電并且計(jì)算能力有限的嵌入式設(shè)備(移動(dòng)手機(jī)、平板等),基于軟件實(shí)現(xiàn)HEVC的實(shí)時(shí)解碼仍然是一個(gè)重要的科研課題。本文實(shí)現(xiàn)了 HEVC官方測(cè)試軟件HM的解碼器并行化,并將其移植到低功耗的具有CPU和GPU的異構(gòu)多處理器片上系統(tǒng)(heterogeneous multiprocessor System-on-Chip)。大量的實(shí)驗(yàn)數(shù)據(jù)表明:GPU的并行架構(gòu)很好的隱藏了解碼器的訪存延時(shí),相對(duì)縮小了視頻幀之間處理時(shí)間的差異。并且,處理各視頻幀的工作量和一個(gè)可以在解碼過(guò)程中方便獲取到的編碼參數(shù)呈現(xiàn)出一致的變化規(guī)律。根據(jù)本文后面章節(jié)說(shuō)明的實(shí)驗(yàn)過(guò)程及相關(guān)實(shí)驗(yàn)結(jié)論,我們提出了 CPU和GPU解碼下一幀的工作量預(yù)測(cè)算法�；陬A(yù)測(cè)得到的工作量,提出了運(yùn)行于實(shí)驗(yàn)平臺(tái)的userspace調(diào)控器下的面向具體應(yīng)用的CPU和GPU協(xié)同DVFS策略。本文提出的DVFS策略有效節(jié)省了解碼HEVC視頻的能量消耗。此外,準(zhǔn)確的工作量預(yù)測(cè)算法使得一個(gè)很小的幀緩沖區(qū)即可保證視頻的實(shí)時(shí)解碼,進(jìn)一步降低了系統(tǒng)的整體開(kāi)銷。
[Abstract]:With the rapid development of network video services, video traffic is gradually dominating the Internet. A plan called Cisco Visual Network Index points out: by 2020. There will be 1 million minutes of video content flowing through the network per second, and global IP video traffic will increase to 82 percent of all IP traffic (businesses and consumers). HD and Ultra HD video are becoming more and more popular. The next generation video coding standard, High Efficiency Video coding. HEVC / H.265) compared with the AVC/H.264 video coding standard, which is widely used now. With the same video quality requirement, higher compression ratio can be achieved. This is mainly due to the addition of many compression techniques to improve the performance of HEVC video coding standards. Such as variable-size coding tree unit, independent parallel coding unit (Tile) and multi-level loop filter, etc. However, these new techniques can improve the efficiency of HEVC standard coding at the same time. It also increases the complexity of video coding and decoding. According to the statistics of the paper, the coding complexity of HEVC standard is increased 5.2 times under the same coding quality. The complexity of the corresponding decoders has increased by 2.1 times. Currently, some top consumer electronics manufacturers, such as Intel Apple, support HEVC coding and decoding via ASIC hardware circuits. However, due to the high computational complexity of the HEVC decoder, embedded devices (mobile phones, tablets, etc.) with limited computing power and battery power. The implementation of real-time decoding of HEVC based on software is still an important research topic. This paper implements the parallelization of HEVC official test software HM decoder. And porting it to a low-power heterogeneous multi-processor system with CPU and GPU. Heterogeneous multiprocessor System-on-Chip). A large number of experimental data show that the parallel architecture of the: GPU can hide the memory access delay of the decoder very well. The difference in processing time between video frames is relatively reduced. And. The workload of processing each video frame and a coding parameter that can be easily obtained in the decoding process show a consistent change rule. According to the experimental process and related experimental conclusions described in the later chapters of this paper. We propose a workload prediction algorithm for the next frame decoded by CPU and GPU. In this paper, an application-oriented CPU and GPU cooperative DVFS strategy based on the userspace governor running on the experimental platform is proposed. The DVFS strategy proposed in this paper effectively saves decoding HEVC. The energy consumption of the video. The accurate workload prediction algorithm enables a small frame buffer to ensure the real-time decoding of the video and further reduces the overall overhead of the system.
【學(xué)位授予單位】：山東大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN919.81;TN764

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