基于UVM的電流監(jiān)控驗(yàn)證平臺(tái)設(shè)計(jì)與實(shí)現(xiàn)
本文關(guān)鍵詞:基于UVM的電流監(jiān)控驗(yàn)證平臺(tái)設(shè)計(jì)與實(shí)現(xiàn) 出處:《西安電子科技大學(xué)》2015年碩士論文 論文類型:學(xué)位論文
更多相關(guān)文章: UVM驗(yàn)證方法學(xué) 事務(wù)級(jí)建模 自我檢測機(jī)制 覆蓋率驅(qū)動(dòng) 可重用性
【摘要】:隨著集成電路設(shè)計(jì)規(guī)模與功能復(fù)雜度不斷提高,造成驗(yàn)證工作復(fù)雜度大幅度提升,驗(yàn)證周期延長到整個(gè)芯片開發(fā)周期70%的時(shí)間,導(dǎo)致驗(yàn)證工作成為集成電路設(shè)計(jì)的主要瓶頸。因此如何提高驗(yàn)證效率,從而減少驗(yàn)證耗時(shí)縮短產(chǎn)品設(shè)計(jì)周期成為目前數(shù)字IC芯片設(shè)計(jì)最棘手的問題。而抽象層次高、可重用性強(qiáng)、自動(dòng)化檢測程度高的驗(yàn)證系統(tǒng)創(chuàng)建將成為提高驗(yàn)證效率的重要途徑。本文通過與傳統(tǒng)驗(yàn)證技術(shù)進(jìn)行對(duì)比得出層次化驗(yàn)證方法的優(yōu)勢(shì)所在,并在此基礎(chǔ)上詳細(xì)對(duì)多種新型層次化驗(yàn)證方法進(jìn)行利弊分析,引出集所有驗(yàn)證方法學(xué)優(yōu)點(diǎn)于一體的UVM驗(yàn)證方法學(xué)。基于事務(wù)級(jí)建模、基于覆蓋率驅(qū)動(dòng)以及基于自我檢測機(jī)制的特點(diǎn)造就UVM驗(yàn)證方法學(xué)能夠?qū)崿F(xiàn)覆蓋率高、靈活性強(qiáng)、驗(yàn)證過程自動(dòng)化程度高、效率高以及可重用性強(qiáng)的驗(yàn)證平臺(tái)。本文對(duì)UVM驗(yàn)證環(huán)境組件UVC、類庫繼承關(guān)系、UVM運(yùn)行機(jī)制以及UVM中優(yōu)秀的通訊機(jī)制進(jìn)行深入分析研究,另外還依據(jù)待測設(shè)計(jì)對(duì)象電流監(jiān)控系統(tǒng)的功能特性以及設(shè)計(jì)結(jié)構(gòu)實(shí)現(xiàn)進(jìn)行驗(yàn)證需求分析,制定驗(yàn)證策略,以UVM驗(yàn)證方法學(xué)為指導(dǎo)搭建了基于UVM的驗(yàn)證平臺(tái)。并采用了基于事務(wù)級(jí)建模、基于自我檢測機(jī)制與基于覆蓋率驅(qū)動(dòng)等方法相結(jié)合的驗(yàn)證手段在制定好的驗(yàn)證情景下對(duì)電流監(jiān)控系統(tǒng)進(jìn)行詳細(xì)驗(yàn)證,最終對(duì)驗(yàn)證仿真結(jié)果與覆蓋率進(jìn)行分析總結(jié)。經(jīng)實(shí)踐證明,本文以UVM驗(yàn)證方法學(xué)為指導(dǎo)搭建的驗(yàn)證平臺(tái),在電流監(jiān)控系統(tǒng)的驗(yàn)證過程中,能夠自動(dòng)化進(jìn)行數(shù)據(jù)比較檢測,及時(shí)定位與報(bào)告錯(cuò)誤信息,并且以基于覆蓋率驅(qū)動(dòng)的方法滿足了驗(yàn)證的覆蓋率要求,驗(yàn)證效率大幅度提升,同時(shí),該平臺(tái)可重用性強(qiáng)的特點(diǎn)使得其在不同的項(xiàng)目中可進(jìn)行復(fù)用。
[Abstract]:As the development of integrated circuit design and function of increased complexity, resulting in verification complexity is greatly improved, verification period is extended to the entire chip development cycle of 70% of the time, resulting in validation work has become a major bottleneck of IC design. So how to improve the verification efficiency, so as to reduce the verification time shorten the cycle of product design has become one of the most difficult digital IC chip design. And the high abstract level, strong reusability, high degree of automation testing verification system creation will become an important way to improve the efficiency of verification. By comparing with the traditional verification technology for comparing the hierarchical verification method advantage, and on the basis of detailed on a variety of new hierarchical verification methods advantages and disadvantages analysis leads to UVM verification method all the verification methodology combines the advantages of learning. Transaction level modeling based on flooding based on coverage The dynamic characteristics and self detection mechanism based on creating UVM verification methodology to achieve high coverage, high flexibility, high degree of automation verification process verification platform, high efficiency and strong reusability. The UVM verification environment for UVC component library of inheritance, in-depth analysis of communication mechanism of excellent UVM mechanism and UVM in addition, according to design object current monitoring system to be tested the function characteristics and structure design verification requirements analysis, formulate verification strategies, UVM verification methodology as a guide to build a verification platform based on UVM. And the transaction level modeling based on self detection mechanism based on coverage driven and method based on the combination of the verification methods detailed verification of the current monitoring system in the validation scenario, the final verification of the simulation results and the coverage rate were analyzed. Proved by practice, based on the UVM verification methodology as a guide to build the verification platform, verification process in current monitoring system, automation data detection, positioning and timely report the error, and the method of coverage driven verification based on meet the coverage requirements, verification efficiency is greatly improved, at the same time. The platform of reusable features that make them can be reused in different projects.
【學(xué)位授予單位】:西安電子科技大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2015
【分類號(hào)】:TN402
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