天堂国产午夜亚洲专区-少妇人妻综合久久蜜臀-国产成人户外露出视频在线-国产91传媒一区二区三区

當前位置:主頁 > 科技論文 > 電子信息論文 >

溫度沖擊載荷下POP堆疊封裝可靠性研究

發(fā)布時間:2018-01-06 08:44

  本文關鍵詞:溫度沖擊載荷下POP堆疊封裝可靠性研究 出處:《江蘇大學》2015年碩士論文 論文類型:學位論文


  更多相關文章: 溫度沖擊 有限元分析 POP堆疊封裝 壽命計算


【摘要】:隨著電子科學和封裝技術的飛速發(fā)展,電子產品的升級和更換更加頻繁。消費者對電子科技類產品的性能需求日益提高,迫使電子封裝密度不斷增大。近年以來電子封裝技術不斷向小尺寸、高密度、高性能等方向發(fā)展。封裝方式也逐漸由二維封裝向空間疊層封裝轉變。疊層封裝POP技術被認為是未來相當長時間內電子封裝技術的主要發(fā)展方向。它是將邏輯運算器件和存儲器件集成在同一封裝體內,不僅在封裝體積沒有增加的情況下提高了封裝密度,而且減小了由封裝線路所帶來的RC延遲。但是由于封裝密度的提高,電子產品在使用過程中熱量更加容易堆積,會對電子產品的可靠性產生嚴重的影響。本文便針對POP堆疊封裝芯片在溫度沖擊載荷下的可靠性進行了實驗和模擬方面的研究。本文的主要工作如下:本文針對POP堆疊封裝結構,對其進行了溫度沖擊載荷下的可靠性模擬,得到了POP堆疊封裝應力應變的分布特點及其隨時間變化規(guī)律;诶碚撚嬎憬Y果預測了焊點的壽命。本文選用了Amkor公司的14mm×14mm的POP封裝芯片作為模擬研究的對象。由于模擬對象為中心對稱結構,本文構建了POP堆疊芯片的1/4模型并對其進行了合理的簡化,并根據(jù)JEDEC的加載標準對其進行了溫度沖擊載荷下的模擬研究。結果表明:在溫度沖擊載荷下整個封裝體的應力主要集中在芯片和焊球上,而整個封裝體的最大應力出現(xiàn)在底層焊球的角端上底層焊球的應力大小呈現(xiàn)出由中心到邊緣逐漸增大的趨勢,而頂層焊球之間的應力大小無明顯的變化趨勢。本文采用了Kencht-Fox焊點壽命預測模型,理論上計算了焊點的疲勞壽命。本文根據(jù)樣品在溫度沖擊載荷下的應變測試原理,搭建了實驗測試平臺。實驗測試了在溫度沖擊載荷下POP堆疊封裝焊點的應變情況。選取了Amkor公司的14mm×14mm與15mm×15mm的兩片封裝體積不同POP堆疊芯片作為實驗對象。對兩個POP堆疊組件的上下兩層封裝焊點在溫度載荷下的應變分別進行了記錄與分析。實驗結果表明:POP堆疊封裝的底層焊點的應變幅要大于頂層焊點的應變幅。在相同溫度載荷下底層封裝焊點的熱可靠性要低于頂層封裝焊點。計算了實驗條件下的焊點壽命并將實驗計算結果與模擬計算結果進行了對比,誤差約為20%,證明其結果具有一定的相似性。對比研究了兩塊封裝體積不同的封裝芯片,結果表明15mm×15mm的封裝芯片其上下層焊點的應變幅分別大于14mm×14mm上下層焊點的應變幅。經計算發(fā)現(xiàn)在相同溫度載荷下15mm×15mm封裝芯片的可靠性低于14mm×14mm封裝芯片的可靠性。表明在相同溫度沖擊載荷下,芯片封裝體積對于焊點的可靠性具有一定的影響,封裝體積越大,焊點可靠性越低。綜上所述,本文針對POP封裝的可靠性進行了實驗與模擬研究,對比分析了在同一溫度沖擊載荷下的模擬與實驗的結果,證明理論模擬的準確性,探尋可以使用數(shù)值模擬的辦法替代實驗測試的可行性。對比分析了在相同溫度載荷下不同封裝體積的POP堆疊芯片的可靠性的情況。其結論可以為三維封裝的可靠性研究提供一定的理論參考,對POP封裝測試和優(yōu)化設計也具有一定的指導和借鑒意義。
[Abstract]:With the rapid development of Electronic Science and technology of electronic packaging, product upgrades and replacement of more frequent. Consumer demand on the performance of electronic technology products increasing, forcing the electronic packaging density increasing. In recent years, electronic packaging technology to small size, high density, high performance and so on. The package mode is gradually change from 2D package to space laminated package. POP package technology stack is considered to be the main development direction in the future for quite a long time in the electronic packaging technology. It is the logical device and the memory device is integrated in the same package, not only in the packaging volume did not increase under the condition of increasing packaging density, but also reduce the brought the packaging line RC delay. But due to the increase of the density of electronic product packaging, heat in the process of using easy accumulation, will have on the reliability of electronic products Seriously affected. This paper is directed to the POP chip stack package reliability in temperature under impact load are studied by experimental and simulation. The main work of this paper is as follows: This paper POP stack package structure to simulate the reliability of temperature under impact load, POP stacked package stress distribution and strain with time changes to the theoretical calculation results. The solder joint life. Based on the object of this paper uses POP's Amkor chip package 14mm * 14mm as simulation study. Because the simulated object centered symmetrical structure, this paper constructs a 1/4 model of POP chip and the stack is simplified reasonably, and according to the the loading of the JEDEC standard has carried on the simulation of temperature under impact load. The results showed that the temperature stress under impact load the whole package mainly focused on chip and welding The ball, and the whole package of the maximum stress appears in the bottom corner of the solder ball on the bottom of the solder ball stress size increased from the center to the edge of the trend, and between the top solder ball stresses have no obvious trend. This paper adopts Kencht-Fox solder joint life prediction model theory to calculate the fatigue life of solder joints. Based on the principle of strain testing samples at temperatures under impact load, built a test platform. The experimental strain POP stacked package solder joints under temperature shock loads. Selected two pieces of different package size POP stacked chip of Amkor company 14mm * 14mm and 15mm * 15mm as the experimental object. The strain two POP stack assembly down two package solder joints under temperature load were recorded and analyzed. The experimental results show that the bottom of the stacked package solder joints of POP strain To be greater than the top spot in the same strain. Under temperature load thermal reliability of solder joints is lower than the bottom of the top package solder joints under the experimental conditions. The calculated and experimental results of fatigue life and the simulation results were compared, the error is about 20%. The results show that a certain similarity. A comparative study of the package two different chip package volume. The results show that the packaged chip 15mm * 15mm of the upper and lower joint strain were more than 14mm * 14mm on the lower joint strain. Found by calculating the reliability at the same temperature under the load of 15mm * 15mm * 14mm chip is lower than that of 14mm chip. In the same temperature shock under load, the chip package volume has certain effect on the reliability of solder joints, the package volume is large, the lower the reliability of solder joints. In summary, this paper aiming at the reliability of POP package The experimental research and simulation, comparative analysis at the same temperature shock loading simulation and experimental results, to prove the accuracy of theoretical simulation, to explore the feasibility of numerical simulation can be used to replace the test. Comparative analysis of the reliability at the same temperature under load with POP stacked chip package size case. The conclusions can provide some theoretical reference for the study on the reliability of the 3D packaging, also has certain guidance and reference for the POP packaging and testing and optimization design.

【學位授予單位】:江蘇大學
【學位級別】:碩士
【學位授予年份】:2015
【分類號】:TN05

【共引文獻】

相關期刊論文 前3條

1 紀偉;劉嚴慶;劉丹;夏志偉;;手動引線鍵合設備夾持臺解決方案[J];電子工業(yè)專用設備;2014年06期

2 戴榮偉;;提高封裝的電子產品電氣性能的環(huán)氧樹脂灌封新工藝[J];電子世界;2014年03期

3 葉樂志;唐亮;劉子陽;;倒裝芯片鍵合技術發(fā)展現(xiàn)狀與展望[J];電子工業(yè)專用設備;2014年11期

,

本文編號:1387156

資料下載
論文發(fā)表

本文鏈接:http://www.sikaile.net/kejilunwen/dianzigongchenglunwen/1387156.html


Copyright(c)文論論文網All Rights Reserved | 網站地圖 |

版權申明:資料由用戶3fcf3***提供,本站僅收錄摘要或目錄,作者需要刪除請E-mail郵箱bigeng88@qq.com