【摘要】：硬件木馬是嵌入在集成電路中的冗余電路單元，能夠在一定條件下激活并導(dǎo)致芯片功能失效或信息泄露，在集成電路設(shè)計(jì)制造的各個(gè)環(huán)節(jié)都有可能被嵌入這種惡意的木馬電路硬件木馬的出現(xiàn)給芯片安全性帶來嚴(yán)重威脅，其相關(guān)檢測(cè)技術(shù)日漸成為信息安全領(lǐng)域的研究熱點(diǎn)，得到了國(guó)際上的廣泛關(guān)注 本文主要開展了基于功耗電磁等側(cè)信道分析技術(shù)的相關(guān)研究工作，首先研究了基于組合邏輯時(shí)序邏輯的硬件木馬載體電路的設(shè)計(jì)方法，重點(diǎn)介紹了組合邏輯型硬件木馬在ISCAS’89基準(zhǔn)電路s713中的植入方法針對(duì)應(yīng)用于IP核版權(quán)保護(hù)中的時(shí)序型硬件木馬激活時(shí)間不足的問題提出了一種改進(jìn)結(jié)構(gòu)，基于高級(jí)加密標(biāo)準(zhǔn)（Advanced Encryption Standard，AES）算法電路驗(yàn)證了這種結(jié)構(gòu)的有效性仿真結(jié)果顯示，，這種方法能夠在電路面積減少0.123%的基礎(chǔ)上使木馬的激活時(shí)間提高約120倍 在此基礎(chǔ)上，設(shè)計(jì)并實(shí)現(xiàn)了基于FPGA的檢測(cè)平臺(tái)，提出了包括降噪小信號(hào)提取等有關(guān)平臺(tái)的驗(yàn)證與優(yōu)化方法，設(shè)計(jì)了硬件木馬的檢測(cè)流程最后介紹了基于側(cè)信道分析的數(shù)據(jù)處理算法，重點(diǎn)針對(duì)主成分分析（Principal ComponentAnalysis, PCA）算法開展研究工作，通過提取基于時(shí)序型硬件木馬的載體電路在木馬激活前后的側(cè)信道信息建立電路的電磁輻射模型，在此基礎(chǔ)之上驗(yàn)證了PCA算法對(duì)于檢測(cè)時(shí)序型硬件木馬的有效性 實(shí)驗(yàn)結(jié)果表明，基于本文所設(shè)計(jì)的硬件木馬檢測(cè)平臺(tái)，PCA算法能夠有效檢測(cè)占電路總面積4%以上的硬件木馬電路
[Abstract]:The hardware Trojan is a redundant circuit unit embedded in the integrated circuit, which can be activated under certain conditions and lead to the failure of the function of the chip or the disclosure of information. In the integrated circuit design and manufacture of each link is likely to be embedded in this malicious Trojan circuit hardware Trojan has brought a serious threat to the security of the chip, its related detection technology has become a research hotspot in the field of information security. This paper mainly focuses on the research of power dissipation electromagnetic equal-side channel analysis technology. Firstly, the design method of hardware Trojan horse carrier circuit based on combinational logic sequential logic is studied. This paper mainly introduces the implanting method of combinational logic hardware Trojan in ISCAS'89 reference circuit s713. Aiming at the problem of insufficient activation time of sequential hardware Trojan used in IP core copyright protection, this paper proposes an improved structure. Based on the advanced encryption standard (Advanced Encryption Standard,AES) algorithm circuit, the simulation results show that the structure is effective. This method can reduce the circuit area by 0.123% and increase the activation time of Trojan horse by about 120 times. On this basis, the detection platform based on FPGA is designed and implemented. In this paper, the verification and optimization methods of related platforms, including noise reduction and small signal extraction, are put forward. The detection flow of hardware Trojan horse is designed. Finally, the data processing algorithm based on side channel analysis is introduced, especially for principal component analysis (Principal ComponentAnalysis,). PCA) algorithm, the electromagnetic radiation model of the circuit is established by extracting the side channel information of the carrier circuit based on the time series hardware Trojan horse before and after the Trojan horse is activated. On this basis, the validity of PCA algorithm for detecting sequential hardware Trojan horse is verified. The experimental results show that, based on the hardware Trojan detection platform designed in this paper, PCA algorithm can effectively detect the hardware Trojan circuit which accounts for more than 4% of the total circuit area.
【學(xué)位授予單位】：天津大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TP393.08

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本文編號(hào)：2319740