基于NetFPGA的路由器功耗優(yōu)化研究
發(fā)布時間：2018-10-08 18:56
【摘要】：在21世紀，隨著科學技術的日益發(fā)展，互聯網已經應用于世界的各個領域。網絡互連設備作為構成互聯網的重要組成部分，其數量飛速增長，伴隨產生的功耗更是不可小視。而在眾多網絡互連設備中，路由器能將不同網絡或者網段之間的數據信息根據路由選擇協議進行選擇而實現轉發(fā)，成為了最重要的網絡互連設備之一，在全球網絡運行中產生的功耗也是十分巨大的。與此同時，出于經濟和環(huán)境方面的考慮，在下一代網絡的研究中已經把能源的充分利用放在越來越重要的地位。因此，通過對路由器結構的研究來降低工作時產生的功耗具有較大的研究價值。 本文首先對路由器功耗優(yōu)化的研究背景進行了介紹，分析了國內外研究現狀，包括在NetFPGA開發(fā)平臺上的研究成果以及對于路由器功耗方面的研究狀況，從而論證了本課題具有一定的可研究性和創(chuàng)新性；之后對基于NetFPGA開發(fā)平臺的基本路由器的工作原理和內部結構進行了深入的研究分析，同時在此基礎上通過硬件設計實現了根據流量自適應調頻的路由器，包括根據外部數據流量統計和路由器內部緩存區(qū)緩存量統計兩種實現自適應調頻方式；最后通過使用功耗測試儀器對路由器各種頻率下所產生的功耗進行測試與比較得出結論。 在深入研究基于NetFPGA開發(fā)平臺的基本路由器的工作原理和內部結構后，本文設計了一種根據流量自適應調頻的路由器來降低其產生的功耗。并提出了根據路由器內部緩存區(qū)緩存量統計和根據外部數據流量統計兩種實現自適應調頻方式，前者是設計了一種緩存流量感知算法來統計當前通過路由器流量的大小，后者是設計了外部接口數據統計模塊來統計當前通過路由器流量的大小。與此同時，對根據流量自適應調頻的路由器進行了硬件電路的設計，包括多頻率產生電路，協調SRAM讀寫電路，兩種調頻機制硬件實現電路等。最終通過搭建的國際上領先的路由器功耗測試平臺，測試兩種調頻機制下路由器功耗優(yōu)化的情況。由于在大部分情況下單位時間內通過路由器的流量都較小，因此本文設計的根據流量自適應調頻路由器都能工作在較小的頻率下，，根據實驗結果所得，在較低工作頻率下工作時路由器產生的功耗比原先不能調頻的路由器下降低15%-20%，有效的降低了路由器產生的功耗。 目前，對于路由器功耗的研究國內外均有相關涉及，然而本文提出的根據流量自適應調頻路由器的硬件電路設計尚未有相關文獻提出，并且本實驗以及功耗測試平臺也具有一定的先進行，因此對該課題的研究有一定創(chuàng)新意義。
[Abstract]:In the 21 st century, with the development of science and technology, the Internet has been applied in every field of the world. As an important part of the Internet, network interconnection devices are increasing rapidly, and the accompanying power consumption can not be underestimated. Among the many network interconnection devices, routers can select and forward the data information between different networks or network segments according to routing protocols, so they become one of the most important network interconnection devices. The power consumption generated in the global network operation is also very large. At the same time, due to economic and environmental considerations, the full use of energy has become more and more important in the next generation network (NGN) research. Therefore, it is of great value to study the structure of router to reduce the power consumption. This paper first introduces the research background of router power optimization, and analyzes the research status at home and abroad, including the research results on NetFPGA development platform and the research status of router power consumption. This paper demonstrates that this subject has certain researchability and innovation, and then makes a deep research and analysis on the working principle and internal structure of the basic router based on NetFPGA development platform. At the same time, the router which adapts to frequency modulation according to the traffic is realized by hardware design, including two ways of realizing adaptive frequency modulation according to the statistics of external data traffic and the cache of the inner buffer of router. Finally, the power consumption generated by the router at various frequencies is tested and compared with the power consumption test instrument. After deeply studying the working principle and internal structure of the basic router based on the NetFPGA development platform, this paper designs a router that adapts to frequency modulation according to the traffic to reduce its power consumption. This paper also proposes two ways to realize adaptive frequency modulation according to the statistics of internal buffer cache and external data traffic. The former is to design a cache traffic sensing algorithm to calculate the current traffic through the router. The latter is the design of external interface data statistics module to count the current traffic through the router size. At the same time, the hardware circuit of the router based on the traffic adaptive frequency modulation is designed, including the multi-frequency generation circuit, the coordinated SRAM reading and writing circuit, the hardware realization circuit of two kinds of FM mechanism and so on. Finally, the router power optimization under two frequency modulation mechanisms is tested by a leading international router power test platform. Because the traffic per unit time is smaller in most cases, the adaptive FM router designed in this paper can work at a lower frequency, according to the experimental results, When the router works at a lower operating frequency, the power consumption generated by the router is 15 to 20 lower than that under the original router without frequency modulation, which effectively reduces the power consumption generated by the router. At present, the research on router power consumption is related at home and abroad. However, the hardware circuit design of adaptive frequency modulation router based on traffic has not been proposed in this paper. And this experiment and the power consumption test platform also has certain first, therefore the research to this topic has the certain innovation significance.
【學位授予單位】：杭州電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP393.05
本文編號：2257901
[Abstract]:In the 21 st century, with the development of science and technology, the Internet has been applied in every field of the world. As an important part of the Internet, network interconnection devices are increasing rapidly, and the accompanying power consumption can not be underestimated. Among the many network interconnection devices, routers can select and forward the data information between different networks or network segments according to routing protocols, so they become one of the most important network interconnection devices. The power consumption generated in the global network operation is also very large. At the same time, due to economic and environmental considerations, the full use of energy has become more and more important in the next generation network (NGN) research. Therefore, it is of great value to study the structure of router to reduce the power consumption. This paper first introduces the research background of router power optimization, and analyzes the research status at home and abroad, including the research results on NetFPGA development platform and the research status of router power consumption. This paper demonstrates that this subject has certain researchability and innovation, and then makes a deep research and analysis on the working principle and internal structure of the basic router based on NetFPGA development platform. At the same time, the router which adapts to frequency modulation according to the traffic is realized by hardware design, including two ways of realizing adaptive frequency modulation according to the statistics of external data traffic and the cache of the inner buffer of router. Finally, the power consumption generated by the router at various frequencies is tested and compared with the power consumption test instrument. After deeply studying the working principle and internal structure of the basic router based on the NetFPGA development platform, this paper designs a router that adapts to frequency modulation according to the traffic to reduce its power consumption. This paper also proposes two ways to realize adaptive frequency modulation according to the statistics of internal buffer cache and external data traffic. The former is to design a cache traffic sensing algorithm to calculate the current traffic through the router. The latter is the design of external interface data statistics module to count the current traffic through the router size. At the same time, the hardware circuit of the router based on the traffic adaptive frequency modulation is designed, including the multi-frequency generation circuit, the coordinated SRAM reading and writing circuit, the hardware realization circuit of two kinds of FM mechanism and so on. Finally, the router power optimization under two frequency modulation mechanisms is tested by a leading international router power test platform. Because the traffic per unit time is smaller in most cases, the adaptive FM router designed in this paper can work at a lower frequency, according to the experimental results, When the router works at a lower operating frequency, the power consumption generated by the router is 15 to 20 lower than that under the original router without frequency modulation, which effectively reduces the power consumption generated by the router. At present, the research on router power consumption is related at home and abroad. However, the hardware circuit design of adaptive frequency modulation router based on traffic has not been proposed in this paper. And this experiment and the power consumption test platform also has certain first, therefore the research to this topic has the certain innovation significance.
【學位授予單位】：杭州電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP393.05
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