【摘要】：同步以太網(wǎng)是一種基于物理層的時鐘同步技術(shù),能夠很好地解決在網(wǎng)絡(luò)1P化過程中,傳統(tǒng)TDM業(yè)務(wù)與分組網(wǎng)絡(luò)之間存在的同步與定時問題。單一的同步以太網(wǎng)只適用于沒有時間同步要求的情況,而對于有時間同步要求的應(yīng)用場景,則通常采用在同步以太網(wǎng)的基礎(chǔ)上結(jié)合IEEE1588V2協(xié)議的方法來實現(xiàn)系統(tǒng)的高精度時間同步要求�；贗EEE1588V2的同步以太網(wǎng)解決了通用以太網(wǎng)延遲時間長且同步能力差的瓶頸,因此受到了業(yè)內(nèi)人士的廣泛關(guān)注。 本文首先研究了分組網(wǎng)絡(luò)中的時鐘同步和時間同步方式,選出了適合于本課題的同步以太網(wǎng)時鐘同步方式和IEEE1588V2時間同步方式。接著,通過對高端路由器系統(tǒng)內(nèi)的時鐘同步和時間同步方案進行分析,提出了高端路由器設(shè)備中時鐘板的功能和主要技術(shù)指標。隨后,制定時鐘板的總體設(shè)計方案,根據(jù)具體方案對芯片進行選型,并設(shè)計了各模塊的硬件電路。最后,對時鐘板上邏輯部分所要實現(xiàn)的功能進行分析,將邏輯劃分為三級時鐘處理、Localbus接口和時間同步處理3大模塊,并對每個模塊的實現(xiàn)方案和時序設(shè)計進行詳細的說明,通過Modelsim仿真的方式驗證了邏輯設(shè)計的正確性。
[Abstract]:Synchronous Ethernet is a kind of clock synchronization technology based on physical layer, which can solve the synchronization and timing problems between traditional TDM services and packet networks in the process of network 1P. A single synchronous Ethernet is only suitable for situations where there is no time synchronization requirement, whereas for applications with time synchronization requirements, Then the high precision time synchronization requirement of the system is usually realized by combining the synchronous Ethernet with IEEE1588V2 protocol. Synchronous Ethernet based on IEEE1588V2 solves the bottleneck of long delay time and poor synchronization ability of general Ethernet, so it has been widely concerned by the industry. In this paper, the clock synchronization and time synchronization in packet networks are studied, and the synchronous Ethernet clock synchronization mode and IEEE1588V2 time synchronization mode are selected. Then, through the analysis of the clock synchronization and time synchronization schemes in the high-end router system, the functions and main technical specifications of the clock board in the high-end router equipment are put forward. Then, the overall design of the clock board is made, the chip is selected according to the specific scheme, and the hardware circuit of each module is designed. Finally, the function of the logic part on the clock board is analyzed, and the logic is divided into three modules: the local bus interface and the time synchronization, and the implementation scheme and timing design of each module are explained in detail. The correctness of logic design is verified by Modelsim simulation.
【學位授予單位】：南京理工大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP393.11

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